Design and Implementation of Multirate Digital Filters

2002 ◽  
pp. 257-292 ◽  
Author(s):  
Hakan Johansson ◽  
Lars Wanhammar

In this chapter we discuss techniques to design and implement multirate digital filters with low power consumption which also allow a reduction in the design effort, since the resulting circuits are highly modular and regular and can relatively easily be incorporated in the normal design flow of commercial tools. First we briefly review techniques that can be applied at various design levels, i.e., from algorithm level down to layout, to reduce the power consumption in CMOS implementations of both digital FIR and IIR filters and are useful in many other DSP algorithms. Second, we discuss the properties of lattice wave digital filters and various techniques to design efficient multirate digital filters for changing the sampling rate by a factor of two. Third, we discuss the design of multistage multirate digital FIR filter structures for arbitrary bandwidths. Finally, we provide some design examples.

Author(s):  
Yue Zhang ◽  
Linwei Tao

In order to realize the acquisition and storage of underwater acoustic signals for aiming at the requirements of multi-channel, low power consumption and small volume for underwater receiver extension of sonar system, a multi-channel signal acquisition and storage system based on FPGA and STM32 with variable number of working channels and sampling frequency is designed, in which the system is consisted of 8 pieces, 8 channel and 24 bits high dynamic range Δ-Σ ADS1278 ADC chip to synchronous multi-channel analog signal acquisition. FPGA, as the acquisition sequence and logic control, reads and collates the ADC chip data and writes it into the internal high-capacity FIFO, and adds corresponding operations according to the characteristics of FIFO in an application. SMT32 single-chip microcomputer reads the FIFO data through the high-speed SPI interface with FPGA and writes the multi-channel data into the high-capacity SD card. The testing results have verified that the system has characteristics such as stable and reliable, easy configuration, low power consumption, can guarantee the multichannel data serial transmission, storage, accurate, up to 64 analog signals at the same time the real-time collection and storage, top 20 kHz sampling rate, the system total power of the system of about 3W, data rates up to 100 Mb/s, fully meet the needs of underwater sound acquisition system.


2018 ◽  
Vol 7 (4) ◽  
pp. 207
Author(s):  
Rasha W. Hamad

In this paper. Bireciprocal Lattice Wave Digital Filters (BLWDFs) are utilized in an  approximate linear-phase in pass-band design of  order IIR wavelet filter banks (FBs). These filter banks are efficiently designed by replacement one of  branches for (BLWDFs)  by only a unit delay. The coefficients of the designed filter are achieved by simulating the IIR response suggested in [1]. The design is  first simulated using Matlab programming in order to investigate the resulting wavelet filter properties and to find the suitable wordlength for the BLWDFs coefficients. FPGA implemtation of the proposed IIR wavelet filter bank is also achived for three levels with less complexity and high operating frequency.


Sign in / Sign up

Export Citation Format

Share Document