Experiments on data processing algorithms: energy efficiency of wireless and untethered field programmable gate array (FPGA)-based embedded systems

Extracted features are widely used for image processing. Many research endeavors have been undertaken to extract significant features of fast moving images. Appropriate algorithm processing is necessary to extract features and provide features to the other modules in real time with low-cost embedded systems. The features from accelerated segment test (FAST) algorithm is renowned for feature extraction. FAST is composed of simple arithmetic operators. In this study, FAST is employed to implement the hardware accelerator in a field-programmable gate array for small embedded systems. Meanwhile, the threshold value in FAST affects the number of extracted features and the execution time. The precarious execution time makes it difficult for the system to schedule the timing of system functions and thus degrades the performance. An appropriate method is necessary to stabilize the execution time. A dynamic threshold controller in a FAST hardware accelerator is thus proposed to enable a stable execution time. A proportional integral controller composed of an adder, subtractor, and shifter is applied for low design implementation costs. The proposed approach occupies 2,263 slice flip-flops, 3,498 look-up tables, and 17 block RAMs in a Xilinx Virtex 5 FX field-programmable gate array. It requires 3.87[Formula: see text]ms for continuous 800×480 images from the KITTI benchmark.

Download Full-text

Hardware Considerations for Tensor Implementation and Analysis Using the Field Programmable Gate Array

Electronics ◽

10.3390/electronics7110320 ◽

2018 ◽

Vol 7 (11) ◽

pp. 320 ◽

Cited By ~ 1

Author(s):

Ian Grout ◽

Lenore Mullin

Keyword(s):

Machine Learning ◽

Field Programmable Gate Array ◽

Digital Signal ◽

Learning Systems ◽

Complex Data ◽

Outer Product ◽

Typical Application ◽

Field Programmable ◽

Processing Algorithms ◽

Gate Array

In today’s complex embedded systems targeting internet of things (IoT) applications, there is a greater need for embedded digital signal processing algorithms that can effectively and efficiently process complex data sets. A typical application considered is for use in supervised and unsupervised machine learning systems. With the move towards lower power, portable, and embedded hardware-software platforms that meet the current and future needs for such applications, there is a requirement on the design and development communities to consider different approaches to design realization and implementation. Typical approaches are based on software programmed processors that run the required algorithms on a software operating system. Whilst such approaches are well supported, they can lead to solutions that are not necessarily optimized for a particular problem. A consideration of different approaches to realize a working system is therefore required, and hardware based designs rather than software based designs can provide performance benefits in terms of power consumption and processing speed. In this paper, consideration is given to utilizing the field programmable gate array (FPGA) to implement a combined inner and outer product algorithm in hardware that utilizes the available hardware resources within the FPGA. These products form the basis of tensor analysis operations that underlie the data processing algorithms in many machine learning systems.

Download Full-text