scholarly journals Design space exploration of Convolutional Neural Networks based on Evolutionary Algorithms

2017 ◽  
Vol 3 (1) ◽  
Author(s):  
Abeer Al-Hyari ◽  
Shawki Areibi
Keyword(s):  
Neural Networks ◽  
Genetic Algorithms ◽  
Evolutionary Algorithms ◽  
Convolutional Neural Networks ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Handwritten Digit ◽  
Fully Connected ◽  
The Given

This paper proposes a framework for design space exploration ofConvolutional Neural Networks (CNNs) using Genetic Algorithms(GAs). CNNs have many hyperparameters that need to be tunedcarefully in order to achieve favorable results when used for imageclassification tasks or similar vision applications. Genetic Algorithmsare adopted to efficiently traverse the huge search spaceof CNNs hyperparameters, and generate the best architecture thatfits the given task. Some of the hyperparameters that were testedinclude the number of convolutional and fully connected layers, thenumber of filters for each convolutional layer, and the number ofnodes in the fully connected layers. The proposed approach wastested using MNIST dataset for handwritten digit classification andresults obtained indicate that the proposed approach is able to generatea CNN architecture with validation accuracy up to 96.66% onaverage.

scholarly journals CNN2Gate: An Implementation of Convolutional Neural Networks Inference on FPGAs with Automated Design Space Exploration

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2200
Author(s):  
Alireza Ghaffari ◽  
Yvon Savaria
Keyword(s):  
Machine Learning ◽  
Neural Networks ◽  
Convolutional Neural Networks ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Automatic Synthesis ◽  
Software Libraries ◽  
Learning Software ◽  
High Level

Convolutional Neural Networks (CNNs) have a major impact on our society, because of the numerous services they provide. These services include, but are not limited to image classification, video analysis, and speech recognition. Recently, the number of researches that utilize FPGAs to implement CNNs are increasing rapidly. This is due to the lower power consumption and easy reconfigurability that are offered by these platforms. Because of the research efforts put into topics, such as architecture, synthesis, and optimization, some new challenges are arising for integrating suitable hardware solutions to high-level machine learning software libraries. This paper introduces an integrated framework (CNN2Gate), which supports compilation of a CNN model for an FPGA target. CNN2Gate is capable of parsing CNN models from several popular high-level machine learning libraries, such as Keras, Pytorch, Caffe2, etc. CNN2Gate extracts computation flow of layers, in addition to weights and biases, and applies a “given” fixed-point quantization. Furthermore, it writes this information in the proper format for the FPGA vendor’s OpenCL synthesis tools that are then used to build and run the project on FPGA. CNN2Gate performs design-space exploration and fits the design on different FPGAs with limited logic resources automatically. This paper reports results of automatic synthesis and design-space exploration of AlexNet and VGG-16 on various Intel FPGA platforms.

scholarly journals Design Space Exploration for YOLO Neural Network Accelerator

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1921
Author(s):  
Hongmin Huang ◽  
Zihao Liu ◽  
Taosheng Chen ◽  
Xianghong Hu ◽  
Qiming Zhang ◽  
...  
Keyword(s):  
Neural Network ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Computation Time ◽  
Memory Bandwidth ◽  
Block Transmission ◽  
Transmission Strategy ◽  
The Neural Network ◽  
The Given

The You Only Look Once (YOLO) neural network has great advantages and extensive applications in computer vision. The convolutional layers are the most important part of the neural network and take up most of the computation time. Improving the efficiency of the convolution operations can greatly increase the speed of the neural network. Field programmable gate arrays (FPGAs) have been widely used in accelerators for convolutional neural networks (CNNs) thanks to their configurability and parallel computing. This paper proposes a design space exploration for the YOLO neural network based on FPGA. A data block transmission strategy is proposed and a multiply and accumulate (MAC) design, which consists of two 14 × 14 processing element (PE) matrices, is designed. The PE matrices are configurable for different CNNs according to the given required functions. In order to take full advantage of the limited logical resources and the memory bandwidth on the given FPGA device and to simultaneously achieve the best performance, an improved roofline model is used to evaluate the hardware design to balance the computing throughput and the memory bandwidth requirement. The accelerator achieves 41.99 giga operations per second (GOPS) and consumes 7.50 W running at the frequency of 100 MHz on the Xilinx ZC706 board.

Sign in / Sign up

Export Citation Format

Share Document