Graphene-based photonic synapse for multi wavelength neural networks

MRS Advances ◽  
2020 ◽  
Vol 5 (37-38) ◽  
pp. 1909-1917
Author(s):  
Bicky A. Marquez ◽  
Hugh Morison ◽  
Zhimu Guo ◽  
Matthew Filipovich ◽  
Paul R. Prucnal ◽  
...  
Keyword(s):  
Neural Networks ◽  
Large Scale ◽  
Current Control ◽  
Microring Resonator ◽  
Core Element ◽  
Energy Applications ◽  
Multi Wavelength ◽  
High Bandwidth ◽  
On Chip ◽  
Synapse Model

AbstractA synapse is a junction between two biological neurons, and the strength, or weight of the synapse, determines the communication strength between the neurons. Building a neuromorphic (i.e. neuron isomorphic) computing architecture, inspired by a biological network or brain, requires many engineered synapses. Furthermore, recent investigation in neuromorphic photonics, i.e. neuromorphic architectures on photonics platforms, have garnered much interest to enable high-bandwidth, low-latency, low-energy applications of neural networks in machine learning and neuromorphic computing. We propose a graphene-based synapse model as a core element to enable large-scale photonic neural networks based on on-chip multiwavelength techniques. This device consists of an electro-absorption modulator embedded in a microring resonator. We also introduce an encoding protocol that allows for the representation of synaptic weights on our photonic device with 15.7 bits of resolution using current control hardware. Recent work has suggested that graphene-based modulators could operate in excess of 100 GHz. Combined with our work, such a graphene-based synapse could enable applications for ultrafast and online learning.

scholarly journals A Scatter-and-Gather Spiking Convolutional Neural Network on a Reconfigurable Neuromorphic Hardware

2021 ◽  
Vol 15 ◽  
Author(s):  
Chenglong Zou ◽  
Xiaoxin Cui ◽  
Yisong Kuang ◽  
Kefei Liu ◽  
Yuan Wang ◽  
...  
Keyword(s):  
Neural Networks ◽  
Large Scale ◽  
Average Power ◽  
Time Step ◽  
Mapping Algorithm ◽  
Learning Tasks ◽  
Main Challenge ◽  
Neuromorphic Hardware ◽  
Average Power Consumption ◽  
On Chip

Artificial neural networks (ANNs), like convolutional neural networks (CNNs), have achieved the state-of-the-art results for many machine learning tasks. However, inference with large-scale full-precision CNNs must cause substantial energy consumption and memory occupation, which seriously hinders their deployment on mobile and embedded systems. Highly inspired from biological brain, spiking neural networks (SNNs) are emerging as new solutions because of natural superiority in brain-like learning and great energy efficiency with event-driven communication and computation. Nevertheless, training a deep SNN remains a main challenge and there is usually a big accuracy gap between ANNs and SNNs. In this paper, we introduce a hardware-friendly conversion algorithm called “scatter-and-gather” to convert quantized ANNs to lossless SNNs, where neurons are connected with ternary {−1,0,1} synaptic weights. Each spiking neuron is stateless and more like original McCulloch and Pitts model, because it fires at most one spike and need be reset at each time step. Furthermore, we develop an incremental mapping framework to demonstrate efficient network deployments on a reconfigurable neuromorphic chip. Experimental results show our spiking LeNet on MNIST and VGG-Net on CIFAR-10 datasetobtain 99.37% and 91.91% classification accuracy, respectively. Besides, the presented mapping algorithm manages network deployment on our neuromorphic chip with maximum resource efficiency and excellent flexibility. Our four-spike LeNet and VGG-Net on chip can achieve respective real-time inference speed of 0.38 ms/image, 3.24 ms/image, and an average power consumption of 0.28 mJ/image and 2.3 mJ/image at 0.9 V, 252 MHz, which is nearly two orders of magnitude more efficient than traditional GPUs.

scholarly journals Toward Robust Cognitive 3D Brain-Inspired Cross-Paradigm System

2021 ◽  
Vol 15 ◽  
Author(s):  
Abderazek Ben Abdallah ◽  
Khanh N. Dang
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Large Scale ◽  
Three Dimensional ◽  
Network On Chip ◽  
Spike Timing ◽  
Dimensional Structure ◽  
Spiking Neural Network ◽  
3D Ics ◽  
On Chip

Spiking Neuromorphic systems have been introduced as promising platforms for energy-efficient spiking neural network (SNNs) execution. SNNs incorporate neuronal and synaptic states in addition to the variant time scale into their computational model. Since each neuron in these networks is connected to many others, high bandwidth is required. Moreover, since the spike times are used to encode information in SNN, a precise communication latency is also needed, although SNN is tolerant to the spike delay variation in some limits when it is seen as a whole. The two-dimensional packet-switched network-on-chip was proposed as a solution to provide a scalable interconnect fabric in large-scale spike-based neural networks. The 3D-ICs have also attracted a lot of attention as a potential solution to resolve the interconnect bottleneck. Combining these two emerging technologies provides a new horizon for IC design to satisfy the high requirements of low power and small footprint in emerging AI applications. Moreover, although fault-tolerance is a natural feature of biological systems, integrating many computation and memory units into neuromorphic chips confronts the reliability issue, where a defective part can affect the overall system's performance. This paper presents the design and simulation of R-NASH-a reliable three-dimensional digital neuromorphic system geared explicitly toward the 3D-ICs biological brain's three-dimensional structure, where information in the network is represented by sparse patterns of spike timing and learning is based on the local spike-timing-dependent-plasticity rule. Our platform enables high integration density and small spike delay of spiking networks and features a scalable design. R-NASH is a design based on the Through-Silicon-Via technology, facilitating spiking neural network implementation on clustered neurons based on Network-on-Chip. We provide a memory interface with the host CPU, allowing for online training and inference of spiking neural networks. Moreover, R-NASH supports fault recovery with graceful performance degradation.

Reducing weight precision of convolutional neural networks towards large-scale on-chip image recognition

2015 ◽  
Author(s):  
Zhengping Ji ◽  
Ilia Ovsiannikov ◽  
Yibing Wang ◽  
Lilong Shi ◽  
Qiang Zhang
Keyword(s):  
Neural Networks ◽  
Convolutional Neural Networks ◽  
Image Recognition ◽  
Large Scale ◽  
On Chip

A Developmental Method for Evolving Large-Scale Spiking Neural Networks

2012 ◽  
Vol 35 (12) ◽  
pp. 2633 ◽  
Author(s):  
Xiang-Hong LIN ◽  
Tian-Wen ZHANG ◽  
Gui-Cang ZHANG
Keyword(s):  
Neural Networks ◽  
Large Scale ◽  
Spiking Neural Networks

scholarly journals A Latency-Optimized Network-on-Chip with Rapid Bypass Channels

Micromachines ◽  
2021 ◽  
Vol 12 (6) ◽  
pp. 621
Author(s):  
Wenheng Ma ◽  
Xiyao Gao ◽  
Yudi Gao ◽  
Ningmei Yu
Keyword(s):  
Great Reduction ◽  
Network On Chip ◽  
Traffic Patterns ◽  
Single Cycle ◽  
High Bandwidth ◽  
On Chip

Network-on-Chips with simple topologies are widely used due to their scalability and high bandwidth. The transmission latency increases greatly with the number of on-chip nodes. A NoC, called single-cycle multi-hop asynchronous repeated traversal (SMART), is proposed to solve the problem by bypassing intermediate routers. However, the bypass setup request of SMART requires additional pipeline stages and wires. In this paper, we present a NoC with rapid bypass channels that integrates the bypass information into each flit. In the proposed NoC, all the bypass requests are delivered along with flits at the same time reducing the transmission latency. Besides, the bypass request is unicasted in our design instead of broadcasting in SMART leading to a great reduction in wire overhead. We evaluate the NoC in four synthetic traffic patterns. The result shows that the latency of our proposed NoC is 63.54% less than the 1-cycle NoC. Compared to SMART, more than 80% wire overhead and 27% latency are reduced.

Sign in / Sign up

Export Citation Format

Share Document