Acceleration of Inter-Task Routing for JIT Compilation Reconfigurable Computing Platform Using Customized Processor

2015 ◽  
Vol 10 (4) ◽  
pp. 380
Author(s):  
Seyedhassan Daryanavard ◽  
Mohammad Eshghi ◽  
Ali Jahanian
Keyword(s):  
Reconfigurable Computing ◽  
Computing Platform ◽  
Jit Compilation

Design and Implement of the Reconfigurable Algorithm Based on uC/OS-II

2012 ◽  
Vol 198-199 ◽  
pp. 1372-1377
Author(s):  
Shu Ping Le ◽  
Zhi Wen Xiong ◽  
Hong Zeng
Keyword(s):  
Operating System ◽  
Reconfigurable Computing ◽  
Scheduling Algorithm ◽  
Program Execution ◽  
Application Development ◽  
Improve Performance ◽  
Computing Platform ◽  
The Status ◽  
Configurable Hardware ◽  
New System

More and more applications need The ability to customize the architecture to match the computation and the data flow of the application, so increasingly new system implementations based on reconfigurable computing are being considered. Reconfigurable computing has potential to accelerate a wide variety of applications; its main feature is the ability to perform computations in hardware to improve performance, while retaining the flexibility of software solutions. An operating system (OS) for reconfigurable computing uses new versions of algorithms for the scheduling, the operating system must decide how to allocate the hardware at run-time based on the status of the system. This paper discusses the scheduling algorithm for reconfigurable computing platform, covers two aspects of reconfigurable computing: architectures and design methods. The tasks are divided into two categories in this survey, consider the issues involved in reusing the configurable hardware during program execution. And improve μC/OS-II to manage the use of reconfigurable resources, responsible for task scheduling, helping the programmer to concentrate more on application development.

scholarly journals A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection

2012 ◽  
Vol 2012 ◽  
pp. 1-14
Author(s):  
Sascha Mühlbach ◽  
Andreas Koch
Keyword(s):  
Reconfigurable Computing ◽  
High Speed ◽  
Computer Users ◽  
Dynamic Partial Reconfiguration ◽  
Malicious Software ◽  
Computing Platform ◽  
Device Architecture ◽  
Network Platform ◽  
Dedicated Hardware ◽  
A Current

Malicious software has become a major threat to computer users on the Internet today. Security researchers need to gather and analyze large sample sets to develop effective countermeasures. The setting of honeypots, which emulate vulnerable applications, is one method to collect attack code. We have proposed a dedicated hardware architecture for honeypots which allows both high-speed operation at 10 Gb/s and beyond and offers a high resilience against attacks on the honeypot infrastructure itself. In this work, we refine the base NetStage architecture for better management and scalability. Using dynamic partial reconfiguration, we can now update the functionality of the honeypot during operation. To allow the operation of a larger number of vulnerability emulation handlers, the initial single-device architecture is extended to scalable multichip systems. We describe the technical aspects of these modifications and show results evaluating an implementation on a current quad-FPGA reconfigurable computing platform.

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