program execution
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2022 ◽  
Vol 22 (2) ◽  
pp. 1-33
Author(s):  
Philipp Kather ◽  
Rodrigo Duran ◽  
Jan Vahrenhold

Previous studies on writing and understanding programs presented evidence that programmers beyond a novice stage utilize plans or plan-like structures. Other studies on code composition showed that learners have difficulties with writing, reading, and debugging code where interacting plans are merged into a short piece of code. In this article, we focus on the question of how different code-composition strategies and the familiarity with code affect program comprehension on a more abstract, i.e., algorithmic level. Using an eye-tracking setup, we explored how advanced students comprehend programs and their underlying algorithms written in either a merged or abutted (sequenced) composition of code blocks of varying familiarity. The effects of familiarity and code composition were studied both isolated and in combination. Our analysis of the quantitative data adds to our understanding of the behavior reported in previous studies and the effects of plans and their composition on the programs’ difficulty. Using this data along with retrospective interviews, we analyze students’ reading patterns and provide support that subjects were able to form mental models of program execution during task performance. Furthermore, our results suggest that subjects are able to retrieve and create schemata when the program is composed of familiar templates, which may improve their performance; we found indicators for a higher element-interactivity for programs with a merged code composition compared to abutted code composition.


2022 ◽  
Vol 54 (9) ◽  
pp. 1-38
Author(s):  
Gábor E. Gévay ◽  
Juan Soto ◽  
Volker Markl

Over the past decade, distributed dataflow systems (DDS) have become a standard technology. In these systems, users write programs in restricted dataflow programming models, such as MapReduce, which enable them to scale out program execution to a shared-nothing cluster of machines. Yet, there is no established consensus that prescribes how to extend these programming models to support iterative algorithms. In this survey, we review the research literature and identify how DDS handle control flow, such as iteration, from both the programming model and execution level perspectives. This survey will be of interest for both users and designers of DDS.


2022 ◽  
Vol Volume 18, Issue 1 ◽  
Author(s):  
Ankush Das ◽  
Frank Pfenning

Traditional session types prescribe bidirectional communication protocols for concurrent computations, where well-typed programs are guaranteed to adhere to the protocols. However, simple session types cannot capture properties beyond the basic type of the exchanged messages. In response, recent work has extended session types with refinements from linear arithmetic, capturing intrinsic attributes of processes and data. These refinements then play a central role in describing sequential and parallel complexity bounds on session-typed programs. The Rast language provides an open-source implementation of session-typed concurrent programs extended with arithmetic refinements as well as ergometric and temporal types to capture work and span of program execution. To further support generic programming, Rast also enhances arithmetically refined session types with recently developed nested parametric polymorphism. Type checking relies on Cooper's algorithm for quantifier elimination in Presburger arithmetic with a few significant optimizations, and a heuristic extension to nonlinear constraints. Rast furthermore includes a reconstruction engine so that most program constructs pertaining the layers of refinements and resources are inserted automatically. We provide a variety of examples to demonstrate the expressivity of the language.


Author(s):  
Amir Antonie ◽  
Andrew Mathus

As a result of the parallel element setting, performance assessment and model construction are constrained. Component functions should be observable without direct connections to programming language, for example. As a result of this, solutions that are constituted interactively at program execution necessitate recyclable performance-monitoring interactions. As a result of these restrictions, a quasi, coarse-grained Performance Evaluation (PE) approach is described in this paper. A performance framework for the application system can be polymerized from these data. To validate the evaluation and model construction techniques included in the validation framework, simplistic elements with well-known optimization models are employed.


2021 ◽  
pp. 519-527
Author(s):  
M. H. Sargolzaei

Application-Specific Instruction-Set Processors (ASIPs) have established their processing power in the embedded systems. Since energy efficiency is one of the most important challenges in this area, coarse-grained reconfigurable arrays (CGRAs) have been used in many different domains. The exclusive program execution model of the CGRAs is the key to their energy efficiency but it has some major costs. The context-switching network (CSN) is responsible for handling this unique program execution model and is also one of the most energy-hungry parts of the CGRAs. In this paper, we have proposed a new method to predict important architectural parameters of the CSN of a CGRA, such as the size of the processing elements (PEs), the topology of the CSN, and the number of configuration registers in each PE. The proposed method is based on the high-level code of the input application, and it is used to prune the design space and increase the energy efficiency of the CGRA. Based on our results, not only the size of the design space of the CSN of the CGRA is reduced to 10%, but also its performance and energy efficiency are increased by about 13% and 73%, respectively. The predicted architecture by the proposed method is over 97% closer to the best architecture of the exhaustive searching for the design space.


Information ◽  
2021 ◽  
Vol 13 (1) ◽  
pp. 3
Author(s):  
Jenny Hyunjung Lee ◽  
Darius Coelho ◽  
Klaus Mueller

Two-dimensional space embeddings such as Multi-Dimensional Scaling (MDS) are a popular means to gain insight into high-dimensional data relationships. However, in all but the simplest cases these embeddings suffer from significant distortions, which can lead to misinterpretations of the high-dimensional data. These distortions occur both at the global inter-cluster and the local intra-cluster levels. The former leads to misinterpretation of the distances between the various N-D cluster populations, while the latter hampers the appreciation of their individual shapes and composition, which we call cluster appearance. The distortion of cluster appearance incurred in the 2-D embedding is unavoidable since such low-dimensional embeddings always come at the loss of some of the intra-cluster variance. In this paper, we propose techniques to overcome these limitations by conveying the N-D cluster appearance via a framework inspired by illustrative design. Here we make use of Scagnostics which offers a set of intuitive feature descriptors to describe the appearance of 2-D scatterplots. We extend the Scagnostics analysis to N-D and then devise and test via crowd-sourced user studies a set of parameterizable texture patterns that map to the various Scagnostics descriptors. Finally, we embed these N-D Scagnostics-informed texture patterns into shapes derived from N-D statistics to yield what we call Cluster Appearance Glyphs. We demonstrate our framework with a dataset acquired to analyze program execution times in file systems.


Micromachines ◽  
2021 ◽  
Vol 12 (12) ◽  
pp. 1450
Author(s):  
Xiang Wang ◽  
Zhun Zhang ◽  
Qiang Hao ◽  
Dongdong Xu ◽  
Jiqing Wang ◽  
...  

The hardware security of embedded systems is raising more and more concerns in numerous safety-critical applications, such as in the automotive, aerospace, avionic, and railway systems. Embedded systems are gaining popularity in these safety-sensitive sectors with high performance, low power, and great reliability, which are ideal control platforms for executing instruction operation and data processing. However, modern embedded systems are still exposing many potential hardware vulnerabilities to malicious attacks, including software-level and hardware-level attacks; these can cause program execution failure and confidential data leakage. For this reason, this paper presents a novel embedded system by integrating a hardware-assisted security monitoring unit (SMU), for achieving a reinforced system-on-chip (SoC) on ensuring program execution and data processing security. This architecture design was implemented and evaluated on a Xilinx Virtex-5 FPGA development board. Based on the evaluation of the SMU hardware implementation in terms of performance overhead, security capability, and resource consumption, the experimental results indicate that the SMU does not lead to a significant speed degradation to processor while executing different benchmarks, and its average performance overhead reduces to 2.18% on typical 8-KB I/D-Caches. Security capability evaluation confirms the monitoring effectiveness of SMU against both instruction and data tampering attacks. Meanwhile, the SoC satisfies a good balance between high-security and resource overhead.


2021 ◽  
Vol 5 (S3) ◽  
Author(s):  
Mario C. Oli

The educational system has been greatly affected by the COVID-19 pandemic which lead to the cancellation of face-to-face classes from different learning institutions in the whole world. Using the descriptive and phenomenological approach, this study determined the programming proficiency level of sophomore computer science students where laboratories were not available and online classes through learning management system was just one of the options to deliver the lessons to the students. It determined the proficiency level of the students across the four indicators (program design, program execution, specification satisfaction and coding structures). Findings revealed that the students have an “advanced skills in computer programming and application” across the different evaluative indicators. It was also found out that the proficiency levels of students based from their groupings do not vary which gave meaningful output of their project. It further manifested that their main concerns or problems in developing the programs are lack of programming skills, insufficient knowledge in programming, weak internet connection, communication barriers among members and the passive participation of members of the group.


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