A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection

Malicious software has become a major threat to computer users on the Internet today. Security researchers need to gather and analyze large sample sets to develop effective countermeasures. The setting of honeypots, which emulate vulnerable applications, is one method to collect attack code. We have proposed a dedicated hardware architecture for honeypots which allows both high-speed operation at 10 Gb/s and beyond and offers a high resilience against attacks on the honeypot infrastructure itself. In this work, we refine the base NetStage architecture for better management and scalability. Using dynamic partial reconfiguration, we can now update the functionality of the honeypot during operation. To allow the operation of a larger number of vulnerability emulation handlers, the initial single-device architecture is extended to scalable multichip systems. We describe the technical aspects of these modifications and show results evaluating an implementation on a current quad-FPGA reconfigurable computing platform.

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A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback

International Journal of Reconfigurable Computing ◽

10.1155/2011/439072 ◽

2011 ◽

Vol 2011 ◽

pp. 1-10 ◽

Cited By ~ 12

Author(s):

John C. Hoffman ◽

Marios S. Pattichis

Keyword(s):

Reconfigurable Computing ◽

High Speed ◽

Direct Memory Access ◽

Operating Conditions ◽

Partial Reconfiguration ◽

Dynamic Partial Reconfiguration ◽

Memory Controller ◽

Dynamically Reconfigurable ◽

Active Feedback ◽

Time Overhead

Dynamically reconfigurable computing platforms provide promising methods for dynamic management of hardware resources, power, and performance. Yet, progress in dynamically reconfigurable computing is fundamentally limited by the reconfiguration time overhead. Prior research in the development of dynamic partial reconfiguration (DPR) controllers has been limited by its use of the Processor Local Bus (PLB). As a result, the bus was unavailable during DPR. This resulted in significant time overhead. To minimize the overhead, we introduce the use of a multiport memory controller (MPMC) that frees the PLB during the reconfiguration process. The processor is thus allowed to switch to other tasks during the reconfiguration operation. This effectively limits the reconfiguration overhead. An interrupt is used to inform the processor when the operation is complete. Therefore, the system can multitask during the reconfiguration operation. Furthermore, to maximize performance, we introduce the use of overclocking with active feedback. During overclocking, the use of active feedback is used to ensure that the device voltage and temperature are within nominal operating conditions. All of these contributions lead to significant performance improvements over current partial reconfiguration subsystems. The portability of the system, demonstrated on the Virtex-4 and the Virtex-5, consists of four different hardware platforms.

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Towards A Multi-FPGA Infrared Simulator

The Journal of Defense Modeling and Simulation Applications Methodology Technology ◽

10.1177/154851290700400404 ◽

2007 ◽

Vol 4 (4) ◽

pp. 343-355 ◽

Cited By ~ 1

Author(s):

Vinay Sriram ◽

David Kearney

Keyword(s):

Homeland Security ◽

Reconfigurable Computing ◽

High Speed ◽

High Performance ◽

Large Scale ◽

Computation Time ◽

Ccd Camera ◽

Hardware Acceleration ◽

Limiting Factor ◽

Scene Simulation

High speed infrared (IR) scene simulation is used extensively in defense and homeland security to test sensitivity of IR cameras and accuracy of IR threat detection and tracking algorithms used commonly in IR missile approach warning systems (MAWS). A typical MAWS requires an input scene rate of over 100 scenes/second. Infrared scene simulations typically take 32 minutes to simulate a single IR scene that accounts for effects of atmospheric turbulence, refraction, optical blurring and charge-coupled device (CCD) camera electronic noise on a Pentium 4 (2.8GHz) dual core processor [7]. Thus, in IR scene simulation, the processing power of modern computers is a limiting factor. In this paper we report our research to accelerate IR scene simulation using high performance reconfigurable computing. We constructed a multi Field Programmable Gate Array (FPGA) hardware acceleration platform and accelerated a key computationally intensive IR algorithm over the hardware acceleration platform. We were successful in reducing the computation time of IR scene simulation by over 36%. This research acts as a unique case study for accelerating large scale defense simulations using a high performance multi-FPGA reconfigurable computer.

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Secure Mechanism for Remote Bitstream Updates of Reconfigurable Computing Platform

Proceedings of the 2013 International Conference on Advanced Computer Science and Electronics Information ◽

10.2991/icaise.2013.37 ◽

2013 ◽

Author(s):

Runfeng Huang ◽

Qinglei Zhou

Keyword(s):

Reconfigurable Computing ◽

Computing Platform

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Design of a current steering DAC for a high speed current mode SAR ADC

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS) ◽

10.1109/icecs.2013.6815449 ◽

2013 ◽

Cited By ~ 5

Author(s):

Abdelrahman Elkafrawy ◽

Jens Anders ◽

Timon Bruckner ◽

Maurits Ortmanns

Keyword(s):

High Speed ◽

Current Mode ◽

Sar Adc ◽

Current Steering ◽

Current Steering Dac ◽

A Current

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Extended Time Machine Design using Reconfigurable Computing for Efficient Recording and Retrieval of Gigabit Network Traffic

Computer Engineering ◽

10.4018/978-1-61350-456-7.ch313 ◽

2012 ◽

pp. 699-709

Author(s):

S. Sajan Kumar ◽

M. Hari Krishna Prasad ◽

Suresh Raju Pilli

Keyword(s):

Network Traffic ◽

Reconfigurable Computing ◽

High Speed ◽

Application Programming Interface ◽

High Volume ◽

Machine Design ◽

Input Output ◽

Time Machine ◽

Application Programming ◽

Programming Interface

Till date there are no systems which promise to efficiently store and retrieve high volume network traffic. Like Time Machine, this efficiently records and retrieves high volume network traffic. The bottleneck of such systems has been to capture packets at such a high speed without dropping and to write a large amount of data to a disk quicklt and sufficiently, without impact on the integrity of the captured data (Ref. Cooke.E., Myrick.A., Rusek.D., & Jahanian.F(2006)). Certain hardware and software parts of the operating system (like drivers, input/output interfaces) cannot cope with such a high volume of data from a network, which may cause loss of data. Based on such experiences the authors have come up with a redesigned implementation of the system which have specialized capture hardware with its own Application Programming Interface for overcoming loss of data and improving efficiency in recording mechanisms.

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