ON LOGIC NETWORKS ALLOWING SHORT SINGLE FAULT DETECTION TESTS UNDER ARBITRARY FAULTS OF GATES

2021 ◽  
pp. 85-100
Author(s):  
K. A. Popkov ◽  
Keyword(s):  
Fault Detection ◽  
Boolean Function ◽  
Logic Gates ◽  
Single Fault ◽  
Logic Network

It is proved that one can implement any non-constant Boolean function in n variables by an irredundant logic network in the basis {&, ⊕, ¬}, containing not more than one dummy input variable and allowing a single fault detection test with length not more than 2n + 3 regarding arbitrary faults of logic gates.

Short single tests for circuits with arbitrary stuck-at faults at outputs of gates

2019 ◽  
Vol 29 (5) ◽  
pp. 321-333
Author(s):  
Kirill A. Popkov
Keyword(s):  
Fault Detection ◽  
Boolean Function ◽  
Diagnostic Test ◽  
List Type ◽  
Single Fault

Abstract The following results are proved: any nonconstant Boolean function may be implemented by an irredundant circuit of gates in the basis {x& y, x, x ⊕ y ⊕ z} admitting a single fault detection test of length at most 2 with respect to arbitrary stuck-at faults at outputs of gates, there exists a six-place Boolean function ψ such that any nonconstant Boolean function may be implemented by an irredundant circuit of gates in the basis {ψ} admitting a single diagnostic test of length at most 3 with respect to arbitrary stuck-at faults at outputs of gates.

A method of synthesis of irredundant circuits admitting single fault detection tests of constant length

2019 ◽  
Vol 29 (1) ◽  
pp. 35-48
Author(s):  
Dmitry S. Romanov ◽  
Elena Yu. Romanova
Keyword(s):  
Fault Detection ◽  
Boolean Function ◽  
Constructive Proof ◽  
List Type ◽  
Combinational Circuit ◽  
Constant Length ◽  
Single Fault ◽  
Inputs And Outputs

Abstract A constructive proof is given that in each of the bases B′ = {x&y, x⊕y, x ∼ y}, B1 = {x&y, x⊕y, 1} any n-place Boolean function may be implemented: by an irredundant combinational circuit with n inputs and one output admitting (under single stuck-at faults at inputs and outputs of gates) a single fault detection test of length at most 16, by an irredundant combinational circuit with n inputs and one output admitting (under single stuck-at faults at inputs and outputs of gates and at primary inputs) a single fault detection test of length at most 2n−2log2 n+O(1); besides, there exists an n-place function that cannot be implemented by an irredundant circuit admitting a detecting test whose length is smaller than 2n−2log2 n − Ω(1), by an irredundant combinational circuit with n inputs and three outputs admitting (under single stuck-at faults at inputs and outputs of gates and at primary inputs) a single fault detection test of length at most 17.

A CAD-Based Approach to Failure Diagnosis of CMOSLSI with Single Fault Using Abnormal IDDQ

1997 ◽  
Author(s):  
M. Sanada
Keyword(s):  
Fault Diagnosis ◽  
Fault Location ◽  
Logic Gates ◽  
Physical Damage ◽  
Logic Simulation ◽  
Single Fault ◽  
Circuit Structure ◽  
Logic State ◽  
Simple Logic ◽  
Diagnosis Technique

Abstract A CAD-based fault diagnosis technique for CMOS-LSI with single fault using abnormal IDDQ has been developed to indicate the presence of physical damage in a circuit. This method of progressively reducingthe faulty portion, works by extracting the inner logic state of each block from logic simulation, and by deriving test vector numbers with abnormal IDDQ. To easily perform fault diagnosis, the hierarchical circuit structure is divided into primitive blocks including simple logic gates. The diagnosis technique employs the comparative operation of each primitive block to determine whether one and the same inner logic state with abnormal IDDQ exists in the inner logic state with normal IDDQ or not. The former block is regarded as normal block and the latter block is regarded as faulty block. The fault of the faulty block can be localized easily by using input logic state simulation. Experimental results on real faulty LSI with 100k gates demonstrated rapid diagnosis times of within ten hours ani reliable extraction of the fault location.

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