Electrical and Chemical Characterization of FIB-Deposited Insulators

The electrical and chemical properties of insulators produced by codeposition of siloxane compounds or TEOS with oxygen in a focused ion beam (FIB) system were investigated. Metal-insulator-metal capacitor structures were fabricated and tested. Specifically, leakage current and breakdown voltage were measured and used to calculate the effective resistance and breakdown field. Capacitance measurements were performed on a subset of the structures. It was found that the siloxanebased FIB-insulators had superior electrical properties to those based on TEOS. Microbeam Rutherford backscattering spectrometry analysis and Fourier transform infrared spectroscopy were used to characterize the films and to help understand the differences in electrical behavior as a function of gas chemistry and deposition conditions. Finally, a comparison is made between the results presented here, previous results for FIB-deposited insulators, and typical thermally-grown gate oxides and interlevel dielectric Si02 insulators.

Transmission Electron Microscopy (TEM) Specimen Preparation Technique using Focused Ion Beam (FIB): Application to Material Characterization of Chemical Vapor Deposition of Tungsten (W) and Tungsten Silicides (WSix)

The specimen preparation technique using focused ion beam (FIB) to generate cross-sectional transmission electron microscopy (XTEM) samples of chemical vapor deposition (CVD) of Tungsten-plug (W-plug) and Tungsten Silicides (WSix) was studied. Using the combination method including two axes tilting[l], gas enhanced focused ion beam milling[2] and sacrificial metal coating on both sides of electron transmission membrane[3], it was possible to prepare a sample with minimal thickness (less than 1000 A) to get high spatial resolution in TEM observation. Based on this novel thinning technique, some applications such as XTEM observation of W-plug with different aspect ratio (I - 6), and the grain structure of CVD W-plug and CVD WSix were done. Also the problems and artifacts of XTEM sample preparation of high Z-factor material such as CVD W-plug and CVD WSix were given and the ways to avoid or minimize them were suggested.

Dendritic Growth Failure of a Mesa Diode

The time delayed failure of a mesa diode is explained on the basis of dendritic growth on the oxide passivated diode side walls. Lead dendrites nucleated at the p+ side Pb-Sn solder metallization and grew towards the n side metallization. The infinitesimal cross section area of the dendrites was not sufficient to allow them to directly affect the electrical behavior of the high voltage power diodes. However, the electric fields associated with the dendrites caused sharp band bending near the silicon-oxide interface leading to electron tunneling across the band gap at velocities high enough to cause impact ionization and ultimately the avalanche breakdown of the diode. Damage was confined to a narrow path on the diode side wall because of the limited influence of the electric field associated with the dendrite. The paper presents experimental details that led to the discovery of the dendrites. The observed failures are explained in the context of classical semiconductor physics and electrochemistry.

BiCMOS Die Sort Yield Improvement from Isolation of a Localized Defect Mechanism and Precision TEM Cross Section

This paper describes how the authors used a combination of focused ion beam (FIB) microprobing, transmission electron microscopy (TEM), and data and process analysis to determine that localized water residue was causing a 6% yield loss at die sort.

Characterization of CMOS Structures (0.6 µm process) Submitted to HBM and COM ESD Stress Tests

In this work, we present new results concerning electrostatic discharge (ESD) robustness of 0.6 μm CMOS structures. Devices have been tested according to both HBM and socketed CDM (sCDM) ESD test procedures. Test structures have been submitted to a complete characterization consisting in: 1) measurement of the tum-on time of the protection structures submitted to pulses with very fast rise times; 2) ESD stress test with the HBM and sCDM models; 3) failure analysis based on emission microscopy (EMMI) and Scanning Electron Microscopy (SEM).

The Application of FIB Voltage-Contrast Technique Combining with TEM on Subtle Defect Analysis: Via Delamination After TC

Novel Focused Ion Beam (FIB) voltage-contrast technique combined with TEM has been used in this study to identify a certain subtle defect mechanism that caused reliability stress failures of a new product. The suspected defect was first isolated to a unique via along the row through electrical testing and layout analysis. Static voltage contrast of FIB cross-section was used to confirm the suspected open defect at the via. Precision Transmission Electron Microscope (TEM) was then used to reveal the detail of the defect. Based on the result, proper process changes were implemented. The failure mode was successfully eliminated and the reliability of the product was greatly improved.

Application of Backside Photo and Thermal Emission Microscopy Techniques to Advanced Memory Devices

Both photo- and thermal emission analysis techniques are used from the backside of the die colocate defect sites. The technique is important in that process and package technologies have made front-side analysis difficult or impossible. Several test cases are documented. Intensity attenuation through the bulk of the silicon does not compromise the usefulness of the technique in most cases.

Interpretation of Sudden Failures in Pump Laser Diodes

The occurrence of sudden failures has been reported for 980 nm SL SQW InGaAs pump lasers. The post-mortem analysis reveals failure modes that are consistent with the formation of defects at the active area. The problem calls for two separate efforts: monitoring the degradation at suitable time resolution and structural characterization of defects. This article reports about the optical power and overall voltage monitoring results during a constant current lifetest, in which "sudden failures" switched off the lasers in a few hours, after 1500 hours of regular life, and about their interpretation based on TEM cross-sectional images across an EBIC-detected high recombination site. The hypothesis that Recombination Enhanced Defect Reaction (REDR) is a suitable mechanism for defect growth in forward biased GaAs-based diodes is proposed and discussed that REDR is the origin of the observed sudden failures, starting from native defects located in "cool" regions.

Application of Laser Scanning Microscope to Analyze Forward Voltage Snapback of Compound Semiconductors

A forward voltage (Vf) snapback phenomenon was observed during the analysis of silicon doped gallium-arsenide (GaAs) light emitting diodes (LEOs). In this paper emphasis is placed on both the techniques used during the analysis and the information obtained. Apart from the standard curve tracer characterizations, and utilization of two microsection techniques, significance is placed on the use of a laser scanning microscope (LSM). The LSM has four main analys is features: photoemission (FE) microscopy, optical beam induced current (OBIC), confocal microscopy and infrared laser scanning microscopy [1]. The analysis of the LEOs utilizes two of these features, PE microscopy and OBlC analysis. These techniques are used in a complementary fashion to analyze the forward voltage snapback. The analysis reveals two independent wafer processing related issues, a junction anomaly and an unintentional phantom junction at the substrate to epi interface. Both phenomena can result in the LED Vf snapback.

An Application of Breakthrough Failure Analysis Techniques in Eliminating Silicon Dislocation Problem in Sub-Micron CMOS Devices

As device interconnect layers increase and transistor critical dimensions decrease below sub-micron to cater for higher speed and higher packing density, various new and subtle failure mechanisms have emerged and are becoming increasingly prevalent. Silicon dislocation is a new failure mechanism that falls in this category and was for the first time, uncovered in submicron multilayered CMOS devices. This mechanism was responsible for a systematic yield problem; identified as the 'centre GFA wafer' functional failure problem. In this paper, several breakthrough failure analysis techniques used to narrow down and identify this new mechanism will be presented. Root cause determination and potential solution to this problem will also be discussed.