Pseudo-System-Level Network-on-Chip Design and Simulation with VHDL: A Comparative Case Study on Simulation Time Trade-Offs
Sergio V. Tota
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Mario R. Casu
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Paolo Motto
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Massimo Ruo Roch
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Maurizio Zamboni
Zhiliang Qian
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Ying Fei Teh
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Chi-Ying Tsui
2016 ◽
Vol 8
(3)
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pp. 137-148
Deewakar Thakyal
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Pushpita Chatterjee
2008 ◽
Vol 41
(3)
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pp. 340-359
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David Atienza
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Federico Angiolini
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Srinivasan Murali
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Antonio Pullini
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Luca Benini
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...
Antoine Scherrer
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Tanguy Risset
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Antoine Fraboulet
Pingqiang Zhou
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Ping-Hung Yuh
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Sachin S. Sapatnekar
2007 ◽
Vol 26
(7)
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pp. 1297-1310
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Rutuparna Tamhankar
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Srinivasan Murali
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Stergios Stergiou
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Antonio Pullini
◽
Federico Angiolini
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...
Keren Bergman
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Luca P. Carloni
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Aleksandr Biberman
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Johnnie Chan
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Gilbert Hendry
Sambangi Ramesh
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Manghnani Hitesh
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Santanu Chattopadhyay
P. Veda Bhanu
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Pranav V. Kulkarni
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Sai Pranavi Avadhanam
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J. Soumya
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Linga Reddy Cenkeramaddi