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The NoCRay Graphic Accelerator: a Case-study for MP-SoC Network-on-Chip Design Methodology
2007 International Symposium on System-on-Chip
◽
10.1109/issoc.2007.4427429
◽
2007
◽
Cited By ~ 1
Author(s):
Sergio V. Tota
◽
Mario R. Casu
◽
Paolo Motto
◽
Massimo Ruo Roch
◽
Maurizio Zamboni
Keyword(s):
Design Methodology
◽
Network On Chip
◽
Chip Design
◽
Graphic Accelerator
◽
On Chip
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Cited By
References
Timing-Error-Tolerant Network-on-Chip Design Methodology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
◽
10.1109/tcad.2007.891371
◽
2007
◽
Vol 26
(7)
◽
pp. 1297-1310
◽
Cited By ~ 16
Author(s):
Rutuparna Tamhankar
◽
Srinivasan Murali
◽
Stergios Stergiou
◽
Antonio Pullini
◽
Federico Angiolini
◽
...
Keyword(s):
Design Methodology
◽
Network On Chip
◽
Timing Error
◽
Chip Design
◽
On Chip
Download Full-text
Pseudo-System-Level Network-on-Chip Design and Simulation with VHDL: A Comparative Case Study on Simulation Time Trade-Offs
Indian Journal of Science and Technology
◽
10.17485/ijst/2016/v9i7/87835
◽
2016
◽
Vol 9
(7)
◽
Cited By ~ 3
Author(s):
Negin Mahani
Keyword(s):
Network On Chip
◽
System Level
◽
Comparative Case Study
◽
Chip Design
◽
Trade Offs
◽
On Chip
◽
Simulation Time
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A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources
2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip
◽
10.1109/vlsisoc.2011.6081674
◽
2011
◽
Author(s):
Zhiliang Qian
◽
Ying Fei Teh
◽
Chi-Ying Tsui
Keyword(s):
Fault Tolerant
◽
Dynamic Reconfiguration
◽
Network On Chip
◽
Chip Design
◽
On Chip
Download Full-text
DIA-TORUS:A Novel Topology for Network on Chip Design
International journal of Computer Networks & Communications
◽
10.5121/ijcnc.2016.8310
◽
2016
◽
Vol 8
(3)
◽
pp. 137-148
Author(s):
Deewakar Thakyal
◽
Pushpita Chatterjee
Keyword(s):
Network On Chip
◽
Chip Design
◽
On Chip
Download Full-text
Network-on-Chip design and synthesis outlook
Integration
◽
10.1016/j.vlsi.2007.12.002
◽
2008
◽
Vol 41
(3)
◽
pp. 340-359
◽
Cited By ~ 79
Author(s):
David Atienza
◽
Federico Angiolini
◽
Srinivasan Murali
◽
Antonio Pullini
◽
Luca Benini
◽
...
Keyword(s):
Network On Chip
◽
Chip Design
◽
Design And Synthesis
◽
On Chip
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On-Chip Processor Traffic Modeling for Network-on-Chip Design
Embedded Multi-Core Systems - Networks-on-Chips
◽
10.1201/9781420079791.ch4
◽
2009
◽
pp. 95-121
Author(s):
Antoine Scherrer
◽
Tanguy Risset
◽
Antoine Fraboulet
Keyword(s):
Network On Chip
◽
Traffic Modeling
◽
Chip Design
◽
On Chip
Download Full-text
Application-specific 3D Network-on-Chip design using simulated allocation
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)
◽
10.1109/aspdac.2010.5419830
◽
2010
◽
Cited By ~ 4
Author(s):
Pingqiang Zhou
◽
Ping-Hung Yuh
◽
Sachin S. Sapatnekar
Keyword(s):
Network On Chip
◽
Chip Design
◽
3D Network
◽
On Chip
◽
Application Specific
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A Design Methodology for Performance Maintenance of 3D Network-on-Chip with Multiplexed Through-Silicon Vias
Proceedings of the 3rd International Workshop on Many-core Embedded Systems - MES '15
◽
10.1145/2768177.2768178
◽
2015
◽
Cited By ~ 1
Author(s):
Mostafa Said
◽
Farhad Mehdipour
◽
Kazuaki Murakami
◽
Mohamed El-Sayed
Keyword(s):
Design Methodology
◽
Network On Chip
◽
Through Silicon Vias
◽
3D Network
◽
On Chip
◽
Silicon Vias
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Design Methodology of Dynamically Reconfigurable Network-on-Chip
Lecture Notes in Electrical Engineering - Communication Systems and Information Technology
◽
10.1007/978-3-642-21762-3_14
◽
2011
◽
pp. 111-116
Author(s):
Haiyun Gu
Keyword(s):
Design Methodology
◽
Network On Chip
◽
Dynamically Reconfigurable
◽
On Chip
Download Full-text
Photonic Network-on-Chip Design
10.1007/978-1-4419-9335-9
◽
2014
◽
Cited By ~ 44
Author(s):
Keren Bergman
◽
Luca P. Carloni
◽
Aleksandr Biberman
◽
Johnnie Chan
◽
Gilbert Hendry
Keyword(s):
Network On Chip
◽
Chip Design
◽
Photonic Network
◽
On Chip
Download Full-text
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