scholarly journals A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm Using Verilog HDL

2021 ◽  
Vol 9 (VII) ◽  
pp. 1876-1879
Author(s):  
Charrith Srinivaas
Keyword(s):  
Advanced Encryption Standard ◽  
Verilog Hdl ◽  
Gate Arrays ◽  
Aes Algorithm ◽  
Hardware Implementations ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Rapid Pace ◽  
Tools And Techniques ◽  
Day By Day

As the technology is getting more and more advanced day by day in a rapid pace the problem for the security of data is also increasing at a very staggering rate. The hackers are equipped with new advanced tools and techniques to break any security system. Hence people are getting even more concerned about their data and data’s security. The data security can be achieved by either software or hardware implementations or both put together working in harmony. In this work Field Programmable Gate Arrays (FPGA) device is used for hardware implementation since these devices are less complex, more flexible and provide and have far greater more efficiency. This work mainly focuses on the hardware execution of one of the security algorithms that is the Advanced Encryption Standard (AES) algorithm which is the most highly used algorithm for Encryption. The AES algorithm is executed on Vivado 2014.2 ISE Design Suite and therefore the results are observed on 28 nanometers (nm) Artix-7 FPGA. This work Mainly discusses the design implementation of the AES algorithm and the resources which are consumed in implementing the AES design on Artix-7 FPGA. The resources which are consumed are as follows- Slice Register (SR), Look-Up Tables (LUTs), Input/Output (I/O) and Global Buffer.

scholarly journals Advanced Encryption Standard for Data Encryption using EDK Environment in FPGA

2019 ◽  
Vol 8 (4) ◽  
pp. 11969-11972
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Data Encryption ◽  
Advanced Encryption Standard ◽  
Gate Arrays ◽  
Aes Algorithm ◽  
Encryption And Decryption ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Efficient Processing

now a day’s VLSI is developing technology as predicted by Moors law which is drastically increasing as per demand one of that is data security for efficient processing so, data encryption and decryption are major play in security for this an advanced encryption standard is there which uses reconfigurable hardware process in this paper field programmable gate arrays (FPGAs) kit of Xilinx based platform in which spartan3E EDK kit is used. Here we analyze the speed of AES algorithm by using this EDK environment where obvious high speed is considerable and with power consumption and throughput exemptions. With micro blaze soft core processer we implement our algorithm of AES by using c coding we configure the hardware structure. EDK tool with one round operation is done and both area utilization and throughput are observed as we are familiar that when area reduces power consumption also reduces.

Approaches for FPGA Design Assurance

2022 ◽  
Vol 15 (3) ◽  
pp. 1-29
Author(s):  
Eli Cahill ◽  
Brad Hutchings ◽  
Jeffrey Goeders
Keyword(s):  
Computer Aided Design ◽  
Fpga Design ◽  
Gate Arrays ◽  
Hardware Implementations ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Custom Hardware ◽  
Aided Design ◽  
Closed Source ◽  
Complex Computer

Field-Programmable Gate Arrays (FPGAs) are widely used for custom hardware implementations, including in many security-sensitive industries, such as defense, communications, transportation, medical, and more. Compiling source hardware descriptions to FPGA bitstreams requires the use of complex computer-aided design (CAD) tools. These tools are typically proprietary and closed-source, and it is not possible to easily determine that the produced bitstream is equivalent to the source design. In this work, we present various FPGA design flows that leverage pre-synthesizing or pre-implementing parts of the design, combined with open-source synthesis tools, bitstream-to-netlist tools, and commercial equivalence-checking tools, to verify that a produced hardware design is equivalent to the designer’s source design. We evaluate these different design flows on several benchmark circuits and demonstrate that they are effective at detecting malicious modifications made to the design during compilation. We compare our proposed design flows with baseline commercial design flows and measure the overheads to area and runtime.

scholarly journals FPGA-Based Controller for a Hybrid Grid-Connected PV/Wind/Battery Power System with AC Load

Energies ◽  
2021 ◽  
Vol 14 (8) ◽  
pp. 2108
Author(s):  
Mohamed Yassine Allani ◽  
Jamel Riahi ◽  
Silvano Vergura ◽  
Abdelkader Mami
Keyword(s):  
Fuzzy Logic ◽  
Hybrid System ◽  
High Voltage ◽  
Field Programmable Gate Arrays ◽  
Energy System ◽  
Maximum Power ◽  
Hybrid Energy ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays

The development and optimization of a hybrid system composed of photovoltaic panels, wind turbines, converters, and batteries connected to the grid, is first presented. To generate the maximum power, two maximum power point tracker controllers based on fuzzy logic are required and a battery controller is used for the regulation of the DC voltage. When the power source varies, a high-voltage supply is incorporated (high gain DC-DC converter controlled by fuzzy logic) to boost the 24 V provided by the DC bus to the inverter voltage of about 400 V and to reduce energy losses to maximize the system performance. The inverter and the LCL filter allow for the integration of this hybrid system with AC loads and the grid. Moreover, a hardware solution for the field programmable gate arrays-based implementation of the controllers is proposed. The combination of these controllers was synthesized using the Integrated Synthesis Environment Design Suite software (Version: 14.7, City: Tunis, Country: Tunisia) and was successfully implemented on Field Programmable Gate Arrays Spartan 3E. The innovative design provides a suitable architecture based on power converters and control strategies that are dedicated to the proposed hybrid system to ensure system reliability. This implementation can provide a high level of flexibility that can facilitate the upgrade of a control system by simply updating or modifying the proposed algorithm running on the field programmable gate arrays board. The simulation results, using Matlab/Simulink (Version: 2016b, City: Tunis, Country: Tunisia, verify the efficiency of the proposed solution when the environmental conditions change. This study focused on the development and optimization of an electrical system control strategy to manage the produced energy and to coordinate the performance of the hybrid energy system. The paper proposes a combined photovoltaic and wind energy system, supported by a battery acting as an energy storage system. In addition, a bi-directional converter charges/discharges the battery, while a high-voltage gain converter connects them to the DC bus. The use of a battery is useful to compensate for the mismatch between the power demanded by the load and the power generated by the hybrid energy systems. The proposed field programmable gate arrays (FPGA)-based controllers ensure a fast time response by making control executable in real time.

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