A.C. Arc Flash Analysis: a new derivation method

Author(s):  
Pietro Antonio Scarpino ◽  
Alberto Reatti ◽  
Francesco Grasso
Keyword(s):  
2020 ◽  
pp. 67-78
Author(s):  
Nandan Kumar ◽  
Sainath Shrikant Pawaskar

Flash fire caused by electric arc is different than that caused by flammable liquids/fumes or combustible dusts. A suitable protective clothing for protection against electric arc-flash must be designed as per Indian weather conditions. Currently available garments are manufactured using two or three layers of woven/nonwoven combinations to achieve higher Hazard Risk Category (HRC) rating (level 3 and above). However, they are heavy and not comfortable to the end users. Savesplash® is a single layer inherent flame-retardant knitted fabric. Its arc rating was determined using ASTM standards. It achieved arc thermal performance value (ATPV) of 41 cal/cm2, breakopen threshold energy (E_BT) of 42 cal/cm2 and heat attenuation factor (HAF) of 94% when tested as per ASTM F1959/F1959M-14 which translated into an arc rating of 41 cal/cm2. This is equivalent to HRC level 4 ratings as per National Fire Protection Association’s NFPA 70E standard (USA). Further, cut and sewn gloves (HM-100) developed using Savesplash® fabric reinforced with leather on palm area achieved ATPV of 63 cal/cm2 and HAF of 94.5% when tested as per ASTM F2675/F2675M-13.


Author(s):  
N. Kuji ◽  
T. Takeda ◽  
S. Nakamura ◽  
Y. Komine

Abstract A new logic-model derivation method for leak faults observed by light-emission microscopy (LEM) or in liquid-crystal analysis (LCA) has been developed to verify those faults by comparing them with failures observed on an LSI tester. Since CMOS devices display various kinds of faulty behavior depending on leak resistance, it is essential to include the effects of this resistance in logic models. Considering that the resistance of leaks observed in LEM and LCA ranges from 10 to 10,000 ohm, the new logic models have been derived so that the leak fault could be easily incorporated into logic simulators without SPICE simulation. The feasibility of the proposed method has been demonstrated by using it to diagnose LEM and LCA faults causing logic failure in a 20k-gate logic LSI circuit.


2000 ◽  
Vol 36 (6) ◽  
pp. 1741-1749 ◽  
Author(s):  
K. Borgwald ◽  
V. Saporita ◽  
T.L. Macalady ◽  
T.E. Neal ◽  
R.L. Doughty

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