A Signature Analysis Method for IC Failure Analysis

A new method of signature analysis is presented and explained. This method of signature analysis can be based on either experiential knowledge of failure analysis, observed data, or a combination of both. The method can also be used on low numbers of failures or even single failures. It uses the Dempster-Shafer theory to calculate failure mechanism confidence. The model is developed in the paper and an example is given for its use.

Localizing Heat-Generating Defects Using Fluorescent Microthermal Imaging

Fluorescent microthermal imaging (FMI) involves coating a sample surface with a thin fluorescent film that, upon exposure to UV light source, emits temperature-dependent fluorescence [1-7]. The principle behind FMI was thoroughly reviewed at the ISTFA in 1994 [8, 9]. In two recent publications [10,11], we identified several factors in film preparation and data processing that dramatically improved the thermal resolution and sensitivity of FMI. These factors include signal averaging, the use of base mixture films, film stabilization and film curing. These findings significantly enhance the capability of FMI as a failure analysis tool. In this paper, we show several examples that use FMI to quickly localize heat-generating defects ("hot spots"). When used with other failure analysis techniques such as focused ion beam (FIB) cross sectioning and scanning electron microscope (SEM) imaging, we demonstrate that FMI is a powerful tool to efficiently identify the root cause of failures in complex ICs. In addition to defect localization, we use a failing IC to determine the sensitivity of FMI (i.e., the lowest power that can be detected) in an ideal situation where the defects are very localized and near the surface.

Signature Analysis: Statistical Models and Their Application to FA

This paper deals with the basic concepts of Signature Analysis and the application of statistical models for its implementation. It develops a scheme for computing sample sizes when the failures are random. It also introduces statistical models that comprehend correlations among failures that fail due to the same failure mechanism. The idea of correlation is important because semiconductor chips are processed in batches. Also any risk assessment model should comprehend correlations over time. The statistical models developed will provide the required sample sizes for the Failure Analysis lab to state "We are A% confident that B% of future parts will fail due to the same signature." The paper provides tables and graphs for the evaluation of such a risk assessment. The implementation of Signature Analysis will achieve the dual objective of improved customer satisfaction and reduced cycle time. This paper will also highlight it's applicability as well as the essential elements that need to be in place for it to be effective. Different examples have been illustrated of how the concept is being used by Failure Analysis Operations (FA) and Customer Quality and Reliability Engineering groups.

Burn-in Failure Analysis of 0.5μm 1MB SRAM: Barrier Glue Layer Cracks and Tungsten Plug “Worm Holes”

A new 0.5 um 1 Megabit SRAM which employed a double metal, triple poly CMOS process with Tungsten plug metal to poly /silicon contacts was introduced. During burn-in of this product, high currents, apparently due to electrical overstress, were experienced. Electrical analysis showed abnormal supply current characteristics at high voltages. Failure analysis identified the sites of the high currents of the bum-in rejects and discovered cracks in the glue layer prior to Tungsten deposition as the root cause of the failure. The glue layer cracks allowed a reaction with the poly/silicon, causing opens at the bottom of contacts. These floating nodes caused high currents and often latch-up during burn-in. Designed experiments in the wafer fab identified an improved glue layer process, which has been implemented. The new process shows improvement in burn in performance as well as outgoing product quality.

A Review of Wet Etch Formulas for Silicon Semiconductor Failure Analysis

WET ETCHING is an important part of the failure analysis of semiconductor devices. Analysis requires etches for the removal, delineation by decoration or differential etching, and study of defects in layers of various materials. Each lab usually has a collection of favored etch recipes. Some of these etches are available premixed from the fab chemical supply. Some of these etches may be unique, or even proprietary, to your company. Additionally, the lab etch recipe list will usually contain a variety of classical "named etches". These recipes, such as Dash Etch, have persisted over time. Although well-reported in the literature, lab lists may not accurately represent these recipes, or contain complete and accurate instructions for their use. Time seems to have erased the understanding of the purpose of additives such as iodine, in some of these formulas. To identify the best etches and techniques for a failure analysis operations, a targeted literature review of articles and patents was undertaken. It was a surprise to find that much of the work was quite old, and originally done with germanium. Later some of these etches were modified for silicon. Much of this work is still applicable today. Two main etch types were found. One is concerned with the thinning and chemical polishing of silicon. The other type is concerned with identifying defects in silicon. Many of the named etches were found to consist of variations in a specific acid system. The acid system has been well characterized with ternary diagrams and 3-D surfaces. The named etches were plotted on this diagram. The original formulas and applications of the named etches were traced to assure accuracy, so that the results claimed by the original authors, may be reproduced in today's lab. The purpose of this paper is to share the condensed information obtained during this literature search. Graphical data has been corrected for modem dimensions. Selectivities have been located and discussed. The contents of more than 25 named etches were spreadsheeted. It was concluded that the best approach to delineation is a two-step etch, using uncomplicated and well-characterized standard formulas. The first step uses a decoration or differential etch technique to define the junctions. Formulations for effective decoration etches were found to be surprisingly simple. The second step uses a selective etch to define the various interconnections and dielectric layers. Chromium compounds can be completely eliminated from these formulas, to meet environmental concerns. This work, originally consisting of 30 pages with 106 references, has been condensed to conform with the formatting requirements of this publication.

Signature Analysis of Package Delamination Using Scanning Acoustic Microscope

Package delaminations are often associated with electrical and package reliability problems in IC devices. Delaminations caused by electrical-over-stress (EOS) and moisture expansion during reflow soldering have shown different delamination patterns. A Scanning Acoustic Microscope (SAM) can be used to detect package delaminations. Understanding these delamination signatures can help us quickly identify the failure cause at an early stage of the failure analysis.

Failure Analysis of Flip-Chip Interconnections Through Acoustic Microscopy

Integration of circuits on semiconductor devices with resulting increase in pin counts is driving the need for improvements in packaging for functionality and reliability. One solution to this demand is the Flip- Chip concept in Ultra Large Scale Integration (ULSI) applications [1]. The flip-chip technology is based on the direct attach principle of die to substrate interconnection.. The absence of bondwires clearly enables packages to become more slim and compact, and also provides higher pin counts and higher-speeds [2]. However, due to its construction, with inherent hidden structures the Flip-Chip technology presents a challenge for non-destructive Failure Analysis (F/A). The scanning acoustic microscope (SAM) has recently emerged as a valuable evaluation tool for this purpose [3]. C-mode scanning acoustic microscope (C-SAM), has the ability to demonstrate non-destructive package analysis while imaging the internal features of this package. Ultrasonic waves are very sensitive, particularly when they encounter density variations at surfaces, e.g. variations such as voids or delaminations similar to air gaps. These two anomalies are common to flip-chips. The primary issue with this package technology is the non-uniformity of the die attach through solder ball joints and epoxy underfill. The ball joints also present defects as open contacts, voids or cracks. In our acoustic microscopy study packages with known defects are considered. It includes C-SCAN analysis giving top views at a particular package interface and a B-SCAN analysis that provides cross-sectional views at a desired point of interest. The cross-section analysis capability gives confidence to the failure analyst in obtaining information from a failing area without physically sectioning the sample and destroying its electrical integrity. Our results presented here prove that appropriate selection of acoustic scanning modes and frequency parameters leads to good reliable correlation between the physical defects in the devices and the information given by the acoustic microscope.

Characterization of Unfilled Tungsten Plugs on a 0.35μm CMOS Multilevel Metallization Process

An investigation into metallization/interconnect failures during the process development phase of an advanced 0.35μm CMOS ASIC process is presented. The corresponding electrical failure signature was electrical shorting on SRAM test arrays and subsequently functional/Iddq failures on product-like test vehicles. Advanced wafer-level failure analysis techniques and equipment were used to isolate and identify the leakage source as shorting of metal lines due to tungsten (W) residue which was originating from unfilled vias. Further cross-section analysis revealed that the failing vias were all exposed to the intermetal dielectric spin-on glass (SOG) material used for filling the narrow spaces between metal lines. The outgassing of the SOG in the exposed regions of the via prior to and during the tungsten plug deposition is believed to be the cause of the unfilled vias. This analysis facilitated further process development in eliminating the failure mechanism and since then no failures of this nature have been observed. The process integration approach used to eliminate the failure is discussed.

Fault Verification Simulation for Light-Emission Microscopy and Liquid-Crystal Analysis

A new logic-model derivation method for leak faults observed by light-emission microscopy (LEM) or in liquid-crystal analysis (LCA) has been developed to verify those faults by comparing them with failures observed on an LSI tester. Since CMOS devices display various kinds of faulty behavior depending on leak resistance, it is essential to include the effects of this resistance in logic models. Considering that the resistance of leaks observed in LEM and LCA ranges from 10 to 10,000 ohm, the new logic models have been derived so that the leak fault could be easily incorporated into logic simulators without SPICE simulation. The feasibility of the proposed method has been demonstrated by using it to diagnose LEM and LCA faults causing logic failure in a 20k-gate logic LSI circuit.