scholarly journals On Directed Edge-Disjoint Spanning Trees in Product Networks, An Algorithmic Approach

2014 ◽  
Vol 11 (2) ◽  
pp. 79
Author(s):  
A.R. Touzene ◽  
K. Day

In (Ku et al. 2003), the authors have proposed a construction of edge-disjoint spanning trees EDSTs in undirected product networks. Their construction method focuses more on showing the existence of a maximum number (n1+n2-1) of EDSTs in product network of two graphs, where factor graphs have respectively n1 and n2 EDSTs. In this paper, we propose a new systematic and algorithmic approach to construct (n1+n2) directed routed EDST in the product networks. The direction of an edge is added to support bidirectional links in interconnection networks. Our EDSTs can be used straightforward to develop efficient collective communication algorithms for both models store-and-forward and wormhole. 

2020 ◽  
Vol 34 (4) ◽  
pp. 2346-2362
Author(s):  
Linyuan Lu ◽  
Zhiyu Wang

2017 ◽  
Vol 88 (4) ◽  
pp. 577-591 ◽  
Author(s):  
Miaomiao Han ◽  
Hong-Jian Lai ◽  
Jiaao Li
Keyword(s):  

2020 ◽  
Author(s):  
Jørgen Bang‐Jensen ◽  
Stéphane Bessy ◽  
Jing Huang ◽  
Matthias Kriesell
Keyword(s):  

2015 ◽  
Vol 81 (1) ◽  
pp. 16-29 ◽  
Author(s):  
Xiaofeng Gu ◽  
Hong-Jian Lai ◽  
Ping Li ◽  
Senmei Yao

2000 ◽  
Vol 01 (02) ◽  
pp. 73-94
Author(s):  
A. FERREIRA ◽  
A. GOLDMAN ◽  
S. W. SONG

In most distributed memory MIMD multiprocessors, processors are connected by a point-to-point interconnection network, usually modeled by a graph where processors are nodes and communication links are edges. Since interprocessor communication frequently constitutes serious bottlenecks, several architectures were proposed that enhance point-to-point topologies with the help of multiple bus systems so as to improve the communication efficiency. In this paper we study parallel architectures where the communication means are constituted solely by buses. These architectures can use the power of bus technologies, providing a way to interconnect much more processors in a simple and efficient manner. We present the hyperpath, hypergrid, hyperring, and hypertorus architectures, which are the bus-based versions of the well used point-to-point interconnection networks. Using (hyper) graph theoretic concepts to model inter-processor communication in such networks, we give optimal algorithms for broadcasting a message from one processor to all the others. For deriving high performance communication patterns we developed a new tool called simplification. The idea is to construct a graph, to be called representative graph, from the original hyper-topology, in such a way that it will become easy to describe and perform communication schemes to the former that will fit to the latter, because the simplification concept also allows us to partially use some already known communication algorithms for usual networks.


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