Post-silicon verification of high-speed interconnections in Elbrus-8CB microprocessor

The article describes the experiments carried out during the post-silicone verification of Elbrus-8CB microprocessor – one of the important stages of the verification process, which mostly determines the possibility of creating high-performance computing systems consisting of several microprocessors of this series. The interprocessor communication channels of the Elbrus-8CB microprocessor were investigated and some hypotheses were put forward about the reasons for their low operating speed. Experiments conducted to validate these hypotheses are made with intermediate conclusions based on their results. The built-in testing mechanism of CEI-6G and PCIe 2.0 physical levels was described alongside with its operating modes and testing algorithm. Several studies were carried out to ensure the correctness of the testing mechanism. This led to modifications of the initial testing method. The final conclusions about the reasons for the incorrect operation of interprocessor communications were made, and recommendations were given to improve the high-speed communications signals attenuation parameters and the level of their interference immunity. The relevance of this study for the production of modern high-performance computing systems can be traced not only in the growing interest of designers to this problem, but also in tightening of the requirements of the physical layers manufacturers.

3G Long Term Evolution Baseband Processing with Application-Specific Processors

Data rates in the upcoming 3G long term evolution (LTE) standard will be manifold when compared to the current universal mobile telecommunications system. Implementing receivers conforming with the high-capacity transmission techniques is challenging due to the complexity and computational requirements of algorithms. In this study, the software defined radio (SDR) is targeted and the four essential baseband functions of the 3G LTE receiver, namely, list sphere decoding, fast Fourier transform, QR decomposition, and turbo decoding, are addressed and the functions are implemented as application specific processors (ASPs). As a result, the design space that describes the essential computational challenges of 3G LTE receivers is clarified and estimates of area, power, and interprocessor communication buffer requirements are presented.