AUTOMATION OF CONSTRUCTION OF A SCHEME FOR SOLVING COMPUTE- INTENSIVE PROBLEMS OF MATHEMATICAL PHYSICS ON SUPERCOMPUTERS

В статье представлен подход к разработке информационно-аналитической системы, помогающей исследователю решать вычислительно сложные задачи математической физики на суперкомпьютерах. Система автоматически строит схему решения задачи по спецификации пользователя, введенной им в режиме диалога. Схема включает наиболее подходящие математические модели для решения задачи, численные методы, алгоритмы и параллельные архитектуры, ссылки на доступные фрагменты параллельного кода, которые пользователь может использовать при разработке собственного кода. Построение схемы осуществляется на основе онтологии проблемной области «Решение вычислительно сложных задач математической физики», онтологии заданной предметной области и экспертных правил, построенных с использованием технологии Semantic Web. The paper presents an approach to the development of an information-analytical system that helps a researcher to solve compute-intensive problems of mathematical physics on supercomputers. The system automatically builds a scheme for solving the problem according to the user's specification entered by him in the dialogue mode. The scheme includes the most suitable mathematical models for solving the problem, numerical methods, algorithms and parallel architectures, links to available fragments of parallel code that the user can use when developing their own code. The construction of the scheme is carried out on the basis of the ontology of the problem area "Solving compute-intensive problems of mathematical physics", the ontology of a given subject area and expert rules built using the Semantic Web technology.

Series Architecture on Hybrid Electric Vehicles: A Review

The use of series architecture nowadays is mainly on hybrid buses. In comparison with series-parallel and parallel architectures, which are usually exploited on medium-size cars, the series architecture allows achieving internal combustion engine higher efficiency. The downside of this architecture, due to a double energy conversion (i.e., mechanical energy converted in electrical energy and electrical energy converted again in mechanical energy), is that additional losses are introduced. For this reason, the parallel and the series/parallel architectures were considered more suitable for hybrid medium-size cars. Nevertheless, the use of new technologies can change this scenario. Regarding storage systems, supercapacitors achieved a significant energy density, and they guarantee much higher efficiency than battery storage. Moreover, the use of wide-bandgap components for power electronic converters, such as silicon carbide devices, assure lower losses. In this scenario, the series architecture can become competitive on medium-size cars. This paper shows a review of various studies performed on this topic.

The automated construction of a scheme for solving compute-intensive problems based on the ontological approach and Semantic Web technologies

This paper describes the tools for supporting researchers in the development of a parallel code. The tools are based on the ontology of the knowledge area “Support for solving compute-intensive problems of mathematical physics on supercomputers”. The main result of these tools operation is a scheme for solving the problem, built according to its specification provided by the user. The scheme includes the most suitable mathematical models for solving the problem, numerical methods, algorithms, and parallel architectures, links to available fragments of a parallel code that the user can use when developing his own code. The scheme construction is carried out on the basis of ontology and expert rules built using the Semantic Web technology.

Area-Time Efficient Two-Dimensional Reconfigurable Integer DCT Architecture for HEVC

In this paper, we present area-time efficient reconfigurable architectures for the implementation of the integer discrete cosine transform (DCT), which supports all the transform lengths to be used in High Efficiency Video Coding (HEVC). We propose three 1D reconfigurable architectures that can be configured for the computation of the DCT of any of the prescribed lengths such as 4, 8, 16, and 32. It is shown that matrix multiplication schemes involving fewer adders can be used to derive parallel architectures for 1D integer DCT of different lengths. A novel transposition buffer is designed to be used for the proposed 2D DCT architecture, which offers double the throughput without increasing the size of the transposition buffer. We determine the optimal pipeline locations in the proposed design through the precise estimation of propagation delays and the critical path so that the area-delay-product is optimized and all the output samples are obtained in the same cycle in spite of the recursive nature of the structure. Implementation results show that the proposed 2D integer DCT architectures provide significantly higher throughput per unit area than the existing designs for HEVC.

Parallelization of the K-Means++ Clustering Algorithm

K-means++ is the clustering algorithm that is created to improve the process of getting initial clusters in the K-means algorithm. The k-means++ algorithm selects initial k-centroids arbitrarily dependent on a probability that is proportional to each data-point distance to the existing centroids. The most noteworthy problem of this algorithm is when running happens in sequential mode, as this reduces the speed of clustering. In this paper, we develop a new parallel k-means++ algorithm using the graphics processing units (GPU) where the Open Computing Language (OpenCL) platform is used as the programming environment to perform the data assignment phase in parallel while the Streaming SIMD Extension (SSE) technology is used to perform the initialization step to select the initial centroids in parallel on CPU. The focus is on optimizations directly targeted to this architecture to exploit the most of the available computing capabilities. Our objective is to minimize runtime while keeping the quality of the serial implementation. Our outcomes demonstrate that the implementation of targeting hybrid parallel architectures (CPU & GPU) is the most appropriate for large data. We have been able to achieve a 152 times higher throughput than that of the sequential implementation of k-means ++.