Modified Distributed Arithmetic Concept for Implementations Targeted at Heterogeneous FPGAs

2010 ◽  
Vol 56 (4) ◽  
pp. 345-350
Author(s):  
Mariusz Rawski

Modified Distributed Arithmetic Concept for Implementations Targeted at Heterogeneous FPGAsDistributed Arithmetic (DA) plays an important role in designing digital signal processing modules for FPGA architectures. It allows replacing multiply-and-accumulate (MAC) operations with combinational blocks. The quality of implementations based on DA strongly depends on efficiency of methods that map combinational DA block into FPGA resources. Since modern FPGAs have heterogeneous structure, there is a need for quality algorithms to target these structures and the need for flexible architecture exploration aiding in appropriate mapping. The paper presents a modification of DA concept that allows for very efficient implementation in heterogeneous FPGA architectures.

Author(s):  
E.B. Solovyeva ◽  
◽  
K.S. Ezerov ◽  
Yu.M. Inshakov ◽  
◽  
...  

A half-wave diode rectifier is represented as a nonlinear circuit to study in a laboratory course of electrical engineering. The control and measurement complex NI ELVIS effectively displays the nonlinear circuit properties using oscillograms and spectrograms of signals. The coefficients of ripples and nonlinear distortions are calculated. They help to evaluate the influence of the circuit parameters on the quality of signal conversion when rectifying and detecting. The advantages of the NI ELVIS complex consist in, for instance, the real-time digital signal processing, the visualization of results, the ergonomic visualization tools. These advantages provide clarity and precision in the presentation of complex nonlinear processes in electrical engineering.


2020 ◽  
Vol 11 (5) ◽  
pp. 270-276
Author(s):  
V. V. Korneev ◽  
◽  
I. E. Tarasov ◽  

The analysis carried out in the article shows the possibility of creating a problem-oriented VLSI, fabricated according to the technological standards of 28 nm or less, for at least one family of digital signal processing problems using similar computing nodes in structure. The use of distributed arithmetic allows one to apply a technique based on performing only those multiplication steps for which non-zero digits are set in the corresponding positions of the filter coefficients. Therefore, the performance of 200 nodes executing 2 steps at 1 GHz is equivalent to approximately 80 GMAC/s/mm2 for 16-bit coefficients. The VLSI architecture view opens up the possibility to study the effectiveness of implementing other families of tasks and refine the architectural parameters for their implementation. The proposed functionality of VLSI computing nodes allows them to be used in various fields of technology, which potentially increases the need for the release of such VLSI.


2014 ◽  
Vol 17 (1) ◽  
pp. 32-38
Author(s):  
Nhat Truong Minh Vu ◽  
Binh Hieu Nguyen ◽  
Nhat Minh Pham ◽  
Thuan Huu Huynh ◽  
Tu Trong Bui ◽  
...  

Text To Speech (TTS) using Hidden Markov Model (HMM) has become popular in recent years. However, because most of such systems were implemented on personal computers (PCs), it is difficult to offer these systems to real applications. In this paper, we present a hardware implementation of TTS based on DSP architecture, which is applicable for real applications. By optimizing hardware architecture, the quality of the DSP-based synthesized speech is nearly identical to that synthesized on PCs.


2015 ◽  
Vol 7 (4) ◽  
pp. 63
Author(s):  
Azeddine Wahbi ◽  
Ahmed Roukhe ◽  
Laamari Hlou

The aim of this paper is to design and simulate an AEC in order to enhance the quality of speech disturbed by echo phenomenon. Therefore, in order to design the normalized adaptive AEC, we have used digital signal processing techniques, especially Simulink embedded functions. Effectiveness of the suggested AEC using adaptive normalized algorithm was verified using Matlab/Simulink software. Finally, our AEC has been tested by using ERLE criteria and the analysis results show more efficiency according to ITU-T recommendation G.168.


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