VLSI Architecture with a Configurable Pipeline

2020 ◽  
Vol 11 (5) ◽  
pp. 270-276
Author(s):  
V. V. Korneev ◽  
◽  
I. E. Tarasov ◽  
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Vlsi Architecture ◽  
Digital Signal ◽  
Distributed Arithmetic ◽  
28 Nm

The analysis carried out in the article shows the possibility of creating a problem-oriented VLSI, fabricated according to the technological standards of 28 nm or less, for at least one family of digital signal processing problems using similar computing nodes in structure. The use of distributed arithmetic allows one to apply a technique based on performing only those multiplication steps for which non-zero digits are set in the corresponding positions of the filter coefficients. Therefore, the performance of 200 nodes executing 2 steps at 1 GHz is equivalent to approximately 80 GMAC/s/mm2 for 16-bit coefficients. The VLSI architecture view opens up the possibility to study the effectiveness of implementing other families of tasks and refine the architectural parameters for their implementation. The proposed functionality of VLSI computing nodes allows them to be used in various fields of technology, which potentially increases the need for the release of such VLSI.

Modified Distributed Arithmetic Concept for Implementations Targeted at Heterogeneous FPGAs

2010 ◽  
Vol 56 (4) ◽  
pp. 345-350
Author(s):  
Mariusz Rawski
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Digital Signal ◽  
Efficient Implementation ◽  
Heterogeneous Structure ◽  
Distributed Arithmetic ◽  
Architecture Exploration ◽  
Flexible Architecture ◽  
Heterogeneous Fpga

Modified Distributed Arithmetic Concept for Implementations Targeted at Heterogeneous FPGAsDistributed Arithmetic (DA) plays an important role in designing digital signal processing modules for FPGA architectures. It allows replacing multiply-and-accumulate (MAC) operations with combinational blocks. The quality of implementations based on DA strongly depends on efficiency of methods that map combinational DA block into FPGA resources. Since modern FPGAs have heterogeneous structure, there is a need for quality algorithms to target these structures and the need for flexible architecture exploration aiding in appropriate mapping. The paper presents a modification of DA concept that allows for very efficient implementation in heterogeneous FPGA architectures.

scholarly journals An efficient architecture of iterative logarithm multiplier

2018 ◽  
Vol 7 (2.16) ◽  
pp. 24 ◽  
Author(s):  
Durgesh Nandan ◽  
Jitendra Kanungo ◽  
Anurag Mahajan
Keyword(s):  
Neural Network ◽  
Image Processing ◽  
Signal Processing ◽  
Digital Signal Processing ◽  
Arrival Time ◽  
Vlsi Architecture ◽  
Digital Signal ◽  
Cmos Technology ◽  
Error Cost

Multiplication is one of important arithmetic component for digital signal processing, neural network and image processing. But, it is well known fact that multiplier has most hardware consuming component out of all arithmetic components. Here, it is given a possible solution by using an efficient VLSI architecture of Mitchell’s algorithm based Iterative Logarithmic Multiplier (ILM) with modified architecture of Leading One Detector (LOD) and seamless pipelined technique. The proposed work is based on the hardware minimization at the same error cost than of previously reported architectures. We use VHDL to design the existing and proposed Mitchell’s algorithm based iterative logarithmic multiplier. Both multipliers design are evaluated with the Synopsys design compiler by using 90 nm CMOS technology and compared the results in terms of Data Arrival Time (DAT), area, power, Area Delay Product (ADP) and energy. The proposed Mitchell's based ILM gives 33.18 %, 39.03 % and 31.62 % less ADP, 25.08 %, 38.08 % and 46.72 % less energy for 8, 16, and 32 bits architecture respectively in comparison of the reported ILM. The importance of LODs and seamless pipeline has been shown in an efficient architecture of Mitchell's based ILM. 

scholarly journals Digital signal processing designing for FPGA architectures

2007 ◽  
Vol 20 (3) ◽  
pp. 437-459 ◽  
Author(s):  
Mariusz Rawski ◽  
Bogdan Falkowski ◽  
Tadeusz Łuba
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Distributed Arithmetic ◽  
Embedded Blocks ◽  
Signal Processing Algorithms ◽  
Signal Processors ◽  
High Degree ◽  
Very High

This paper presents the discussion on efficiency of different implementation methodologies of DSP algorithms targeted for modern FPGA architectures. Modern programmable structures are equipped with specialized DSP embedded blocks that allow implementing digital signal processing algorithms with use of the methodology known from digital signal processors. On the first place however, programmable architectures give the designer the possibility to increase efficiency of designed system by exploitation of parallelism of implemented algorithms. Moreover, it is possible to apply special techniques such as distributed arithmetic (DA) that will boost the performance of designed processing systems. Additionally, application of the functional decomposition based methods, known to be best suited for FPGA structures allows utilizing possibilities of programmable technology in very high degree. The paper presents results of comparison of different design approaches in this area.

Sign in / Sign up

Export Citation Format

Share Document