64 Channel ASIC for Neurobiology Experiments

2010 ◽  
Vol 56 (4) ◽  
pp. 375-380 ◽  
Author(s):  
Paweł Gryboś ◽  
Piotr Kmon ◽  
Robert Szczygieł ◽  
Mirosław Żołądź

64 Channel ASIC for Neurobiology ExperimentsThis paper presents the design and measurements of 64 channel Application Specific Integrated Circuits (ASIC) for recording signals in neurobiology experiments. The ASIC is designed in 180 nm technology and operates with ± 0.9 V supply voltage. Single readout channel is built of AC coupling circuit at the input and two amplifier stages. In order to reduce the number of output lines, the 64 analogue signals from readout channels are multiplexed to a single output by an analogue multiplexer. The gain of the single channel can be set either to 350 V/V or 700 V/V. The low and the high cut-off frequencies can be tuned in 9 ÷ 90 Hz and in the 1.6 ÷ 24 kHz range respectively. The input referred noise is 7 μV rms in the bandwidth 90 Hz - 1.6 kHz and 9 μV rms in the bandwidth 9 Hz - 24 kHz. The single channel consumes 200 μW of power and this together with other parameters make the chip suitable for recording neurobiology signals.

MRS Bulletin ◽  
1993 ◽  
Vol 18 (6) ◽  
pp. 46-51 ◽  
Author(s):  
S.P. Murarka ◽  
J. Steigerwald ◽  
R.J. Gutmann

Continuing advances in the fields of very-large-scale integration (VLSI), ultralarge-scale integration (ULSI), and gigascale integration (GSI), leading to the continuing development of smaller and smaller devices, have continually challenged the fields of materials, processes, and circuit designs. The existing metallization schemes for ohmic contacts, gate metal, and interconnections are inadequate for the ULSI and GSI era. An added concern is the reliability of aluminum and its alloys as the current carrier. Also, the higher resistivity of Al and its use in two-dimensional networks have been considered inadequate, since they lead to unacceptably high values of the so-called interconnection delay or RC delay, especially in microprocessors and application-specific integrated circuits (ICs). Here, R refers to the resistance of the interconnection and C to the total capacitance associated with the interlayer dielectric. For the fastest devices currently available and faster ones of the future, the RC delay must be reduced to such a level that the contribution of RC to switching delays (access time) becomes a small fraction of the total, which is a sum of the inherent device delay associated with the semiconductor, the device geometry and type, and the RC delay.


2021 ◽  
Author(s):  
Michael Mattioli

<div>Field-programmable gate arrays (FPGAs) are remarkably versatile. FPGAs are used in a wide variety of applications and industries where use of application-specific integrated circuits (ASICs) is less economically feasible. Despite the area, cost, and power challenges designers face when integrating FPGAs into devices, they provide significant security and performance benefits. Many of these benefits can be realized in client compute hardware such as laptops, tablets, and smartphones.</div>


2003 ◽  
Author(s):  
Steffen Chemnitz ◽  
Heiko Schafer ◽  
Stephanie Schumacher ◽  
Volodymyr Koziy ◽  
Alexander Fischer ◽  
...  

Author(s):  
Rajesh K. Karmani ◽  
Gul Agha ◽  
Mark S. Squillante ◽  
Joel Seiferas ◽  
Marian Brezina ◽  
...  

2010 ◽  
Vol 128 (4) ◽  
pp. 2381-2381
Author(s):  
Armando Jiménez Flores ◽  
Maximino Peña Guerrero ◽  
Jose J. Negrete Redondo

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