The Evolution of Organosilicon Precursors for Low-k Interlayer Dielectric Fabrication Driven by Integration Challenges

Since the application of silicon materials in electronic devices in the 1950s, microprocessors are continuously getting smaller, faster, smarter, and larger in data storage capacity. One important factor that makes progress possible is decreasing the dielectric constant of the insulating layer within the integrated circuit (IC). Nevertheless, the evolution of interlayer dielectrics (ILDs) is not driven by a single factor. At first, the objective was to reduce the dielectric constant (k). Reduction of the dielectric constant of a material can be accomplished by selecting chemical bonds with low polarizability and introducing porosity. Moving from silicon dioxide, silsesquioxane-based materials, and silica-based materials to porous silica materials, the industry has been able to reduce the ILDs’ dielectric constant from 4.5 to as low as 1.5. However, porous ILDs are mechanically weak, thermally unstable, and poorly compatible with other materials, which gives them the tendency to absorb chemicals, moisture, etc. All these features create many challenges for the integration of IC during the dual-damascene process, with plasma-induced damage (PID) being the most devastating one. Since the discovery of porous materials, the industry has shifted its focus from decreasing ILDs’ dielectric constant to overcoming these integration challenges. More supplementary precursors (such as Si-C-Si structured compounds), deposition processes (such as NH3 plasma treatment), and post porosity plasma protection treatment (P4) were invented to solve integration-related challenges. Herein, we present the evolution of interlayer dielectric materials driven by the following three aspects, classification of dielectric materials, deposition methods, and key issues encountered and solved during the integration phase. We aim to provide a brief overview of the development of low-k dielectric materials over the past few decades.

Interface Trap Charge Effects of Monolithic 3D Junctionless Field-Effect Transistors (JLFET) Inverter

We investigated the effect of the interface trap charge in a monolithic three-dimensional inverter structure composing of JLFETs (M3DINV-JLFET), using the interface trap charge distribution extracted in the previous study. The effect of interface trap charge was compared with a conventional M3DINV composing of MOSFETs (M3DINV-MOSFETs) by technology computer-aided design simulation. When the interface trap charges in both M3DINV-JLFET and M3DINV-MOSFET are added, the threshold voltages, on-current levels, and subthreshold swings of both JLFETs and MOSFETs increase, decrease, and increase, respectively, and switching voltages and propagation delays of M3DINV are shifted and increased, respectively. However, since JLFET and MOSFET have different current paths of bulk and interface in channel, respectively, MOSFET is more affected by the interface trap, and M3DINV-JLFET has almost less effect of interface trap at different thickness of interlayer dielectric, compared to M3DINV-MOSFET.

Electrical Coupling for Monolithic 3-D Integrated Circuit Consisting of Feedback Field-Effect Transistors

In this study, for two cases of monolithic 3-dimensional integrated circuit (M3DIC) consisting of vertically stacked feedback field-effect transistors (FBFETs), the variation of electrical characteristics of the FBFET was presented in terms of electrical coupling by using technology computer aided design (TCAD) simulation. In the Case 1, the M3DIC was composed with an N-type FBFET in an upper tier (tier2) and a P-type FBFET in a lower tier (tier1), and in the Case 2, it was composed with the FBFETs of opposite type of the Case 1 on each tier. To utilize the FBFET as a logic device, the study on optimal structure of FBFET was first performed in terms of reducing a memory window. Based on the N-type FBFET, the memory window was investigated with different values of doping concentration and length of channel region divided into two regions. The threshold voltage, capacitance, and transconductance of two cases of M3DIC composed with proposed FBFET were investigated for different thickness of an interlayer dielectric (TILD). In the Case 1, only for reverse sweep, the threshold voltage of FBFET in the tier2 was changed significantly at TILD < 15 nm, and the capacitance and transconductance of FBFET in the tier2 changed significantly at TILD < 20 nm, as bottom gate voltage applied with 0 and 1 V. In the Case 2, the electrical characteristics of FBFET in the tier2 changed greater than Case 1 with different TILD.

All-carbocycle hydrocarbon thermosets with high thermal stability and robust mechanical strength for low-k interlayer dielectrics

The development of modern microelectronic industry calls for low permittivity interlayer dielectric materials with excellent thermal stabilities, robust mechanical strength and matching processability. Traditionally, it is difficult to fabricate materials...

STRUCTURAL AND ELECTROPHYSICALLY PERFECT SILICONSAPPHIRE HETEROPAIRS WITH A HIGH-K INTERLAYER DIELECTRIC

This work investigates the features of the formation of a silicon-sapphire interlayer heterointerface obtained by direct splicing, both with an intermediate amorphous dielectric (Hf, Zr, Al; AlN oxides) and without it. The results of structural and electrophysical studies of these structures are presented.

Reliability Simulation of Cu/Polymer interface in Fan-out Wafer Level Packaging

In order to improve the performance and reliability of the package, the interlayer dielectric (Polymer) must not be delaminated and materials should not fracture due to thermal stresses during the operation or the manufacturing process. If the reliability of the package can be known in advance by simulation, it can be expected to greatly help in material selection and package design. Firstly, we created material-specific master curves (time–temperature superposition) by considering the measurement results of the Peel Test at the Cu/Polymer interface and the mechanical properties of polymer. The critical Energy Release Rate (𝒢𝒸) could be calculated by its master curve. Secondary, we calculated the Energy Release Rate (𝒢) from Finite Element Analysis (FEA) in the package model structure. Finally, delamination is judged by normalizing 𝒢/𝒢𝒸. This study has made it possible to simulate the delamination possibility of Cu/Polymer interface at arbitrary temperatures and displacement rates from basic material data and FEA analysis of the package model structure.