The design and implementation of high-speed real-time optical OFDM transmission based on an IMDD system

2014 ◽  
Author(s):  
Luo wei Zhang
Keyword(s):  
Real Time ◽  
High Speed ◽  
Design And Implementation ◽  
Optical Ofdm

Design and Implementation of a High-Speed Real-Time Position Detection System in Electromagnetic Coil Launcher

2020 ◽  
Vol 48 (9) ◽  
pp. 3203-3210
Author(s):  
Guan Xiao Cun ◽  
Shuai Wang ◽  
Denghua Guo ◽  
Shaohua Guan ◽  
Baolong Liu ◽  
...  
Keyword(s):  
Real Time ◽  
High Speed ◽  
Detection System ◽  
Electromagnetic Coil ◽  
Design And Implementation ◽  
Position Detection ◽  
Time Position

Real-Time Digital Signal Processing for High-Speed Coherent Optical OFDM Synchronization

2015 ◽  
Vol 33 (11) ◽  
pp. 2294-2302 ◽  
Author(s):  
Hae Young Rha ◽  
Chun Ju Youn ◽  
Yong-Hwan Kwon ◽  
Hae-Wook Choi
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Real Time ◽  
High Speed ◽  
Digital Signal ◽  
Optical Ofdm ◽  
Ofdm Synchronization

scholarly journals Online digital offset mismatch compensation for high-speed time-interleaved ADC in real-time optical OFDM receiver

2019 ◽  
Vol 27 (12) ◽  
pp. 16650 ◽  
Author(s):  
Ming Chen ◽  
Gang Liu ◽  
Long Zhang ◽  
Hui Zhou ◽  
QingHui Chen
Keyword(s):  
Real Time ◽  
High Speed ◽  
Optical Ofdm ◽  
Interleaved Adc ◽  
Time Interleaved

Design and Implementation of Floyd-Steinberg Algorithm Based on FPGA

2015 ◽  
Vol 738-739 ◽  
pp. 350-353
Author(s):  
Jun Yang ◽  
Zong Jing Li ◽  
Wen Long Li
Keyword(s):  
Real Time ◽  
High Speed ◽  
Complex Multiplication ◽  
Error Diffusion ◽  
Computation Complexity ◽  
Time Error ◽  
Verilog Hdl ◽  
Memory Space ◽  
Design And Implementation ◽  
Quartus Ii

In this paper, we put forward an innovation method of high-speed and real-time error diffusion, which is based on Floyd-Steinberg algorithm. The design introduces LUT(look up table) and pipeline technology instead of complex multiplication operations, which accesses to the memory frequently. The whole design uses Verilog HDL language to program and Quartus ii 8.0 to synthesize and layout. At the end of the paper, we use a 48 pixel as an example, then simulate and verify it on the Modesim, which can prove the correctness of the design. Compared with the standard Floyed-Steinberg algorithm, this design can reduce the computation complexity, use a smaller memory space to exchange lots of logic units and increase the throughput of the algorithm. Besides, it has the advantages of good reconfigurability, simple hardware structure and high real-time.

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