scholarly journals Modern Video Coding: Methods, Challenges and Systems

2021 ◽  
Vol 16 (2) ◽  
pp. 1-12
Author(s):  
Roberta De Carvalho Nobre Palau ◽  
Bianca Santos da Cunha Silveira ◽  
Robson André Domanski ◽  
Marta Breunig Loose ◽  
Arthur Alves Cerveira ◽  
...  
Keyword(s):  
Video Coding ◽  
High Throughput ◽  
High Efficiency ◽  
High Efficiency Video Coding ◽  
Ultrahigh Resolution ◽  
Daily Lives ◽  
Open Research ◽  
Hardware Architectures ◽  
Increasing Demand ◽  
Dedicated Hardware

With the increasing demand for digital video applications in our daily lives, video coding and decoding become critical tasks that must be supported by several types of devices and systems. This paper presents a discussion of the main challenges to design dedicated hardware architectures based on modern hybrid video coding formats, such as the High Efficiency Video Coding (HEVC), the AOMedia Video 1 (AV1) and the Versatile Video Coding (VVC). The paper discusses eachstep of the hybrid video coding process, highlighting the main challenges for each codec and discussing the main hardware solutions published in the literature. The discussions presented in the paper show that there are still many challenges to be overcome and open research opportunities, especially for the AV1 and VVC codecs. Most of these challenges are related to the high throughput required for processing high and ultrahigh resolution videos in real time and to energy constraints of multimedia-capable devices.

scholarly journals H.265 Intra-Picture Prediction Acceleration using Low Complexity Model

2019 ◽  
Vol 8 (11) ◽  
pp. 2939-2944
Keyword(s):  
Video Coding ◽  
High Efficiency ◽  
Low Complexity ◽  
Video Encoding ◽  
High Efficiency Video Coding ◽  
Tree Model ◽  
Time Saving ◽  
Applied Machine Learning ◽  
Additional Burden ◽  
Increasing Demand

H.265 also called High Efficiency Video Coding is the new futuristic international standard proposed by Joint collaboration Team on Video Coding and released in 2013 in the view of constantly increasing demand of video applications. This new standard reduces the bitrate to half as compared to its predecessor H.264 at the expense of huge amount of computational burden on the encoder. In the proposed work we focus on intraprediction phase of video encoding where 33 new angular modes are introduced in addition to DC and Planar mode in order to achieve high quality videos at higher resolutions. We have proposed the use of applied machine learning to HEVC intra prediction to accelerate angular mode decision process. The features used are also low complexity features with minimal computation so as to avoid any additional burden on the encoder. The Decision tree model built is simple yet efficient which is the requirement of the complexity reduction scenario. The proposed method achieves substantial average encoding time saving of 86.59%, with QP values 4,22,27,32 respectively with minimal loss of 0.033 of PSNR and 0.0023 loss in SSIM which makes it suitable for acceptance of High Efficiency Video coding in real time applications

scholarly journals Low-Cost and High-Throughput Hardware Design for the HEVC 16x16 2-D DCT Transform

2014 ◽  
Vol 9 (1) ◽  
pp. 25-35
Author(s):  
Ruhan Conceição ◽  
José Cláudio De Souza Jr ◽  
Ricardo Jeske ◽  
Bruno Zatt ◽  
Marcelo Porto ◽  
...  
Keyword(s):  
Video Coding ◽  
High Throughput ◽  
High Efficiency ◽  
Low Cost ◽  
Hardware Design ◽  
High Efficiency Video Coding ◽  
High Definition ◽  
Real Time Processing ◽  
Dct Transform ◽  
Control Overhead

This article presents the hardware design of the 16x16 2-D DCT used in the new video coding standard, the HEVC – High Efficiency Video Coding. The transforms stage is one of the innovations proposed by HEVC, since a variable size transforms stage is available (from 4x4 to 32x32), allowing the use of transforms with larger dimensions than used in previous standards. The presented design explores the 2-D DCT separability property, using two instances of the one-dimension DCT. The architecture focuses on low hardware cost and high throughput, thus the HEVC 16-points DCT algorithm was simplified targeting a more efficient hardware implementation. Operations and hardware minimization strategies were used in order to achieve such simplifications: operation reordering, factoring, multiplications to shift-adds conversion, and sharing of common sub-expressions. The 1-D DCT architectures were designed in a fully combinational way in order to reduce control overhead. A transposition buffer is used to connect the two 1-D DCT architectures. The synthesis was directed to Stratix III FPGA and TSMC 65nm standard cells technologies. The complete 2-D DCT architecture is able to achieve real-time processing for high and ultra-high definition videos, such as Full HD, QFHD and UHD 8K. When compared with related works, the architectures designed in this work reached the highest throughput and the lowest hardware resources consumption.

1-D Integer Transform for HEVC Encoder Using DSP Slices on FPGA

2015 ◽  
Vol 781 ◽  
pp. 151-154 ◽  
Author(s):  
Pancheewa Arayacheeppreecha ◽  
Suree Pumrin ◽  
Boonchuay Supmonchai
Keyword(s):  
Video Coding ◽  
High Throughput ◽  
High Efficiency ◽  
General Purpose ◽  
Integer Transform ◽  
High Efficiency Video Coding ◽  
Maximum Throughput ◽  
Fpga Architecture ◽  
Sharing Scheme ◽  
Pioneer Research

This paper presents an FPGA architecture for the 1-D integer transform of the latest video coding standard, the High Efficiency Video Coding (HEVC). The design employs hard multipliers in dedicated DSP slices, which are already embedded into an FPGA die, to gain high throughput and save general purpose LUTs. The proposed architecture can support 4x4, 8x8, 16x16, and 32x32 transform. A multiplier sharing scheme is introduced to reduce the total number of required DSP slices in order to be able to fit the design onto a Spartan-3A FPGA. The design can reach a maximum throughput of 1,692 Msamples/s irrespective of the transform size, which is enough to encode 8K (7680x4320) videos at 30 fps. This work is a pioneer research that utilizes the dedicated multipliers on FPGAs in the design of the HEVC transform.

High-Performance Hardware Interpolation Architecture for High Efficiency Video Coding Decoder

2016 ◽  
Vol 11 (9) ◽  
pp. 764
Author(s):  
Lella Aicha Ayadi ◽  
Nihel Neji ◽  
Hassen Loukil ◽  
Mouhamed Ali Ben Ayed ◽  
Nouri Masmoudi
Keyword(s):  
Video Coding ◽  
High Performance ◽  
High Efficiency ◽  
High Efficiency Video Coding
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