scholarly journals Synthesis of Zinc - Bismuth Complex Oxide and Experimental Analysis of Its Magnetic and Electrical Characteristics

Author(s):  
Shirui Weng ◽  
Xianyi Zhang
2020 ◽  
Vol 1004 ◽  
pp. 830-836 ◽  
Author(s):  
Nick Yun ◽  
Justin Lynch ◽  
Woong Je Sung

This paper aims to provide detailed experimental results of 4H-SiC vertical and lateral MOSFETs fabricated on the same 6-inch substrate using a single process flow. The cell optimization and fabrication scheme of both vertical and lateral MOSFETs are described in this paper. The measured electrical characteristics from both structures such as on-resistance, transconductance, threshold voltage, breakdown voltage, and capacitances are discussed. Resistance distribution and figure-of-merits of [Ron×Ciss], [Ron×Coss], and [Ron×Crss] for vertical and lateral MOSFETs are compared to further improve the characteristic of the lateral MOSFET.


2006 ◽  
Vol 43 ◽  
pp. 686-689 ◽  
Author(s):  
Seong Eun Yang ◽  
Duck Kweon Bae ◽  
Hyoungku Kang ◽  
Min Cheol Ahn ◽  
Dong Keun Park ◽  
...  

Author(s):  
F. M. Ross ◽  
R. Hull ◽  
D. Bahnck ◽  
J. C. Bean ◽  
L. J. Peticolas ◽  
...  

We describe an investigation of the electrical properties of interfacial dislocations in strained layer heterostructures. We have been measuring both the structural and electrical characteristics of strained layer p-n junction diodes simultaneously in a transmission electron microscope, enabling us to correlate changes in the electrical characteristics of a device with the formation of dislocations.The presence of dislocations within an electronic device is known to degrade the device performance. This degradation is of increasing significance in the design and processing of novel strained layer devices which may require layer thicknesses above the critical thickness (hc), where it is energetically favourable for the layers to relax by the formation of misfit dislocations at the strained interfaces. In order to quantify how device performance is affected when relaxation occurs we have therefore been investigating the electrical properties of dislocations at the p-n junction in Si/GeSi diodes.


Author(s):  
A.M. Letsoalo ◽  
M.E. Lee ◽  
E.O. de Neijs

Semiconductor devices require metal contacts for efficient collection of electrical charge. The physics of these metal/semiconductor contacts assumes perfect, abrupt and continuous interfaces between the layers. However, in practice these layers are neither continuous nor abrupt due to poor nucleation conditions and the formation of interfacial layers. The effects of layer thickness, deposition rate and substrate stoichiometry have been previously reported. In this work we will compare the effects of a single deposition technique and multiple depositions on the morphology of indium layers grown on (100) CdTe substrates. The electrical characteristics and specific resistivities of the indium contacts were measured, and their relationships with indium layer morphologies were established.Semi-insulating (100) CdTe samples were cut from Bridgman grown single crystal ingots. The surface of the as-cut slices were mechanically polished using 5μm, 3μm, 1μm and 0,25μm diamond abrasive respectively. This was followed by two minutes immersion in a 5% bromine-methanol solution.


Sign in / Sign up

Export Citation Format

Share Document