Fault Localization of a Scan Shift Problem on Integrated Logic Designs

Effort and complexity for failure analysis are increasing on state of the art logic designs. As chips become more and more complex, functional tests are not possible anymore [1] and are replaced with automatic test pattern generation (ATPG) using a full scan design approach. Analysis of failing devices, however, becomes more complex as scan chains contain a large number of flip flops and localization of the failing net is a prerequisite for subsequent physical failure analysis (PFA). This becomes especially true for flip chip products, since access to the chip front side is not easily possible any more. This report describes the necessary failure analysis steps in order to identify the root cause of scan shift problems associated with two products fabricated in deep sub-micron technology