Enabling Electro-Optical Failure Analysis within Extreme Compression Test Architecture

2016 ◽  
Author(s):  
Rudolf Schlangen ◽  
Jon Colburn ◽  
Joe Sarmiento ◽  
Bala Tarun Nelapatla ◽  
Puneet Gupta
Keyword(s):  
Failure Analysis ◽  
Compression Test ◽  
Test Pattern ◽  
Pattern Generation ◽  
Output Data ◽  
Test Compression ◽  
Test Loop ◽  
On Chip ◽  
Test Architecture

Abstract Driven by the need for higher test-compression, increasingly many chip-makers are adopting new DFT architectures such as “Extreme-Compression” (XTR, supported by Synopsys) with on-chip pattern generation and MISR based compression of chain output data. This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA) within the XTR test architecture.

A SIC PAIR GENERATOR FOR A BILBO ENVIRONMENT

2006 ◽  
Vol 15 (05) ◽  
pp. 739-756 ◽  
Author(s):  
I. VOYIATZIS ◽  
D. KEHAGIAS
Keyword(s):  
Test Pattern ◽  
Pattern Generation ◽  
Vlsi Circuits ◽  
Practice Test ◽  
Logic Block ◽  
Efficient Alternative ◽  
Single Input ◽  
Self Test ◽  
On Chip ◽  
Cmos Vlsi

Built-In Self Test (BIST) techniques are commonly used as an efficient alternative to external testing in today's high-complexity VLSI chips since they provide on-chip test pattern generation and response verification. Among the BIST techniques, Built-In Logic Block Observation (BILBO) has been widely used in practice. Test patterns generated by BILBO structures target the detection of stuck-at faults. It has been shown that most common failure mechanisms that appear into current CMOS VLSI circuits cannot be modeled as stuck-at faults. These mechanisms, modeled by sequential (i.e., stuck-open and delay) faults models, require the application of two-pattern tests (vector pairs) in the circuit-under-test inputs. Single Input Change (SIC) pairs are pairs of patterns where the second pattern differs from the first in only one bit and have been successfully used for two-pattern testing. In this paper we present the BILBO-oriented SIC pair Generator technique that extends BILBO in order to generate SIC pairs; in this way, sequential faults are also detected.

An On-Chip Clock Controller for Testing Fault in System on Chip

2013 ◽  
Vol 347-350 ◽  
pp. 724-728
Author(s):  
Wei Lin ◽  
Wen Long Shi
Keyword(s):  
Integrated Circuit ◽  
Test Pattern ◽  
Fault Coverage ◽  
System On Chip ◽  
Pattern Generation ◽  
Integrated Circuit Design ◽  
Scan Test ◽  
High Efficient ◽  
Transition Delay ◽  
On Chip

In this paper, an on-chip clock (OCC) controller with bypass function based on an internal phase locked loop (PLL) is designed to test the faults in system on chip (SOC), such as the transition-delay faults and the stuck-at faults. A clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by the automatic test pattern generation (ATPG) tools. Next, the scan test pattern is simulated by the Synopsys tool and the correctness of the design is verified. The result shows that the design of at-speed scan test in this paper is high efficient for detecting the timing-related defects. Finally, the 89.29 percent transition-delay fault coverage and the 94.50 percent stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design.

scholarly journals An Efficient Test Pattern Generation Scheme for an On Chip BIST

VLSI Design ◽  
2001 ◽  
Vol 12 (4) ◽  
pp. 551-562 ◽  
Author(s):  
B. K. S. V. L. Varaprasad ◽  
L. M. Patnaik ◽  
H. S. Jamadagni ◽  
V. K. Agrawal
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Pattern ◽  
Circuit Simulation ◽  
Cost Effective ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Space Applications ◽  
Efficient Test ◽  
On Chip

Testing and power consumption are becoming two critical issues in VLSI design due to the growing complexity of VLSI circuits and remarkable success and growth of low power applications (viz. portable consumer electronics and space applications). On chip Built In Self Test (BIST) is a cost-effective test methodology for highly complex VLSI devices like Systems On Chip. This paper deals with cost-effective Test Pattern Generation (TPG) schemes in BIST. We present a novel methodology based on the use of a suitable Linear Feedback Shift Register (LFSR) which cycles through the required sequences (test vectors) aiming at a desired fault coverage causing minimum circuit toggling and hence low power consumption while testing. The proposed technique uses circuit simulation data for modeling. We show how to identify the LFSR using graph theory techniques and compute its feedback coefficients (i.e., its characteristic polynomial) for realization of a Test Pattern Generator.

scholarly journals Efficient Test Application for Core-Based Systems Using Twisted-Ring Counters

VLSI Design ◽  
2001 ◽  
Vol 12 (4) ◽  
pp. 475-486
Author(s):  
Anshuman Chandra ◽  
Krishnendu Chakrabarty ◽  
Mark C. Hansen
Keyword(s):  
Test Pattern ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Testing Time ◽  
Automatic Test Pattern Generation ◽  
Test Quality ◽  
Efficient Test ◽  
Test Application ◽  
Test Sets ◽  
Test Architecture

We present novel test set encoding and pattern decompression methods for core-based systems. These are based on the use of twisted-ring counters and offer a number of important advantages–significant test compression (over 10X in many cases), less tester memory and reduced testing time, the ability to use a slow tester without compromising test quality or testing time, and no performance degradation for the core under test. Surprisingly, the encoded test sets obtained from partially-specified test sets (test cubes) are often smaller than the compacted test sets generated by automatic test pattern generation programs. Moreover, a large number of patterns are applied test-per-clock to cores, thereby increasing the likelihood of detecting non-modeled faults. Experimental results for the ISCAS benchmark circuits demonstrate that the proposed test architecture offers an attractive solution to the problem of achieving high test quality and low testing time with relatively slower, less expensive testers.

Fault Localization of a Scan Shift Problem on Integrated Logic Designs

2003 ◽  
Author(s):  
C. Burmer ◽  
P. Egger ◽  
A. Huber ◽  
H. Cerva ◽  
D. Petit ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Test Pattern ◽  
Pattern Generation ◽  
Automatic Test Pattern Generation ◽  
Functional Tests ◽  
Scan Design ◽  
Root Cause ◽  
Full Scan ◽  
Integrated Logic

Abstract Effort and complexity for failure analysis are increasing on state of the art logic designs. As chips become more and more complex, functional tests are not possible anymore [1] and are replaced with automatic test pattern generation (ATPG) using a full scan design approach. Analysis of failing devices, however, becomes more complex as scan chains contain a large number of flip flops and localization of the failing net is a prerequisite for subsequent physical failure analysis (PFA). This becomes especially true for flip chip products, since access to the chip front side is not easily possible any more. This report describes the necessary failure analysis steps in order to identify the root cause of scan shift problems associated with two products fabricated in deep sub-micron technology

Statistical Evaluation of Scan Test Diagnosis Results for Yield Enhancement of Logic Designs

2005 ◽  
Author(s):  
Christian Burmer ◽  
Hans-Peter Erb ◽  
Andreas LemMger ◽  
Markus Gruetzner ◽  
Thomas Schwemboeck ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Statistical Approach ◽  
Test Pattern ◽  
Statistical Evaluation ◽  
Standard Test ◽  
Pattern Generation ◽  
Yield Enhancement ◽  
Diagnostic Features ◽  
Analysis Strategies ◽  
Set Up

Abstract During yield ramp, quick turnaround times between production failures and the results of physical failure analysis are essential. In spite of the growing complexity of today's logic designs, a fast defect localization can be done by using diagnostic features implemented within standard test pattern generation tools. The diagnosis result can not only be used for fault localization but also for statistical analysis based on a large number of failing chips. This statistical approach enables the search for systematic yield detractors and leads to a faster product or technology ramp. This paper describes the necessary steps in order to set up statistical scan diagnosis, discusses the main failure analysis strategies and gives experimental results.

Reduction of the Transferred Test Data Amount

2011 ◽  
pp. 460-475
Author(s):  
Ondrej Novák
Keyword(s):  
Test Data ◽  
Mixed Mode ◽  
Ad Hoc ◽  
Test Pattern ◽  
Test Compression ◽  
On Chip ◽  
Test Vectors

The chapter deals with compression and-or compaction of the ATPG test vectors and their decompression with the help of on-chip automata. The authors describe ad-hoc test compression methods and compression techniques using subsidiary data from an ATPG. Another possibility of test data amount reduction is to use mixed-mode BIST methods that generate patterns in an autonomous built-in TPG together with deterministic patterns from a tester for a CUT exercising. The authors describe different automata that can generate deterministic test patterns after seeding by a deterministic seed. It is shown that these methods can be similarly efficient as test pattern decompressing automata. The described methods are compared according to their efficiency and the most common test compression techniques used by industrial compression tools are shown.

An efficient on-chip deterministic test pattern generation scheme

1989 ◽  
Vol 26 (3) ◽  
pp. 195-204 ◽  
Author(s):  
Aloke K. Das ◽  
P. Pal Chaudhuri
Keyword(s):  
Test Pattern ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
On Chip
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