Study on the Strip Warpage Issues Encountered in the Flip-Chip Process

This study successfully established a strip warpage simulation model of the flip-chip process and investigated the effects of structural design and process (molding, post-mold curing, pretreatment, and ball mounting) on strip warpage. The errors between simulated and experimental values were found to be less than 8%. Taguchi analysis was employed to identify the key factors affecting strip warpage, which were discovered to be die thickness and substrate thickness, followed by mold compound thickness and molding temperature. Although a greater die thickness and mold compound thickness reduce the strip warpage, they also substantially increase the overall strip thickness. To overcome this problem, design criteria are proposed, with the neutral axis of the strip structure located on the bump. The results obtained using the criteria revealed that the strip warpage and overall strip thickness are effectively reduced. In summary, the proposed model can be used to evaluate the effect of structural design and process parameters on strip warpage and can provide strip design guidelines for reducing the amount of strip warpage and meeting the requirements for light, thin, and short chips on the production line. In addition, the proposed guidelines can accelerate the product development cycle and improve product quality with reduced development costs.

3D TSV hybrid pixel detector modules with ATLAS FE-I4 readout electronic chip

The through silicon via (TSV) technology has been introduced in a wide range of electronic packaging applications. Hybrid pixel detectors for X-ray imaging and for high-energy physics (HEP) can benefit from this technology as well. A 3D TSV prototype using the ATLAS FE-I4 readout electronic chip is described in this paper. This type of readout chip is already prepared for the TSV backside process providing a TSV landing pad in the first metal layer of the backend-of-line (BEOL) layer stack. Based on this precondition a TSV backside via-last process is developed on ATLAS FE-I4 readout chip wafer. The readout chip wafers were thinned to 100 µm and 80 µm final thickness and straight sidewall vias with 60 µm in diameter has been etched into the silicon from wafer backside using deep reactive ion etching (DRIE). The filling of the TSVs and the formation of the wafer backside interconnection were provided by a copper electroplating process. ATLAS FE-I4 readout chips with through silicon vias has been successfully tested, tuned and operated. In addition, hybrid pixel detector modules have been flip chip bonded using ATLAS FE-I4 TSV readout chips and planar sensor chips. After mounting the bare modules onto a support PCB, its full functionality has been verified with a source scan.

Analytical and numerical analyses of filling progression and void formation in flip-chip underfill encapsulation process

Purpose This paper aims to study the filling progression of underfill flow and void formation during the flip-chip encapsulation process. Design/methodology/approach A new parameter of filling progression that relates volume fraction filled to filling displacement was formulated analytically. Another indicative parameter of filling efficiency was also introduced to quantify the voiding fraction in filling progression. Additionally, the underfill process on different flip-chips based on the past experiments was numerically simulated. Findings All findings were well-validated with reference to the past experimental results, in terms of quantitative filling progression and qualitative flow profiles. The volume fraction filled increases monotonically with the filling displacement and thus the filling time. As the underfill fluid advances, the size of the void decreases while the filling efficiency increases. Furthermore, the void formed during the underfilling flow stage was caused by the accelerated contact line jump at the bump entrance. Practical implications The filling progression enabled manufacturers to forecast the underfill flow front, as it advances through the flip-chip. Moreover, filling progression and filling efficiency could provide quantitative insights for the determination of void formations at any filling stages. The voiding formation mechanism enables the prompt formulation of countermeasures. Originality/value Both the filling progression and filling efficiency are new indicative parameters in quantifying the performance of the filling process while considering the reliability defects such as incomplete filling and voiding.