scholarly journals Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures

2021 ◽  
Author(s):  
Anita Tino
Keyword(s):  
Tabu Search ◽  
Network On Chip ◽  
Computational Time ◽  
Multiprocessor System ◽  
Case Scenario ◽  
Worst Case ◽  
Multi Objective ◽  
And Performance ◽  
On Chip ◽  
Application Specific

Network-on-Chip (NoC) communication interconnects have emerged as a solution to complex heterogeneous core systems such as those found in Multiprocessor System-on-Chip architectures. Many previous works have used the objectives of power or performance during topology synthesis for regular or application specific based NoC design. However, given the crucial requirements and demands of future on-chip applications, it is imperative that designs consider both power and performance aspects, in addition to other important system constraints. Therefore, in order to address such issues, this thesis work presents a multi-objective Tabu search based topology synthesis technique for designing power and performance efficient Network-on-Chip architectures. The methodology incorporates an analytical and simulation approach in order to compromise between computational time and effort within the algorithm. Furthermore, this work also presents a novel approach for a power and performance tradeoff during contention and deadlock removal within synthesis. The proposed method was tested using seven different multimedia and network benchmark application, where results displayed an increase in performance and decrease in power dissipation in comparison to other previous application specific and regular mesh designs. The analysis method was successful during topology generation, yielding an overall accuracy rate deviation of 19.8% within the worst case scenario.

scholarly journals Multi-objective Tabu search based topology synthesis for designing power and performance efficient NoC architectures

2021 ◽  
Author(s):  
Anita Tino
Keyword(s):  
Tabu Search ◽  
Network On Chip ◽  
Computational Time ◽  
Multiprocessor System ◽  
Case Scenario ◽  
Worst Case ◽  
Multi Objective ◽  
And Performance ◽  
On Chip ◽  
Application Specific

Network-on-Chip (NoC) communication interconnects have emerged as a solution to complex heterogeneous core systems such as those found in Multiprocessor System-on-Chip architectures. Many previous works have used the objectives of power or performance during topology synthesis for regular or application specific based NoC design. However, given the crucial requirements and demands of future on-chip applications, it is imperative that designs consider both power and performance aspects, in addition to other important system constraints. Therefore, in order to address such issues, this thesis work presents a multi-objective Tabu search based topology synthesis technique for designing power and performance efficient Network-on-Chip architectures. The methodology incorporates an analytical and simulation approach in order to compromise between computational time and effort within the algorithm. Furthermore, this work also presents a novel approach for a power and performance tradeoff during contention and deadlock removal within synthesis. The proposed method was tested using seven different multimedia and network benchmark application, where results displayed an increase in performance and decrease in power dissipation in comparison to other previous application specific and regular mesh designs. The analysis method was successful during topology generation, yielding an overall accuracy rate deviation of 19.8% within the worst case scenario.

scholarly journals Network-On-Chip Topology Generation and Analysis For Transaction-Based Systems-on-Chip

2021 ◽  
Author(s):  
Victor. Dumitriu
Keyword(s):  
Design Method ◽  
Prediction Method ◽  
Network On Chip ◽  
Network Resources ◽  
Case Scenario ◽  
Worst Case ◽  
Networks On Chip ◽  
Analysis And Design ◽  
Systems On Chip ◽  
On Chip

The Network-on-Chip concept is emerging as a promising new method of addressing the communication requirements of complex Systems-on-Chip. However, network design at this level must take into consideration the specific communication protocols of on-chip components. This thesis presents a topology analysis and design method for networks-on-chip based on the transaction-oriented protocols common to on-chip systems. The generated topologies target the latency of critical links in the system, while the analysis method can predict the degree of contention in a system prior to the simulation phase. The proposed topologies are tested using various applications, including and MPEG4 Decoder, and are found to perform the same or better than regular topologies, while using less network resources. The contention prediction method is found to be accurate to within 27% in the worst case scenario.

scholarly journals Power and Signal-to-Noise Ratio Optimization in Mesh-Based Hybrid Optical Network-on-Chip using Semiconductor Optical Amplifiers

2019 ◽  
Vol 9 (6) ◽  
pp. 1251 ◽  
Author(s):  
Jun Yeong Jang ◽  
Min Su Kim ◽  
Chang-Lin Li ◽  
Tae Hee Han
Keyword(s):  
Optical Amplifiers ◽  
Signal To Noise Ratio ◽  
Optical Network ◽  
Semiconductor Optical Amplifiers ◽  
Network On Chip ◽  
Laser Source ◽  
Crosstalk Noise ◽  
Worst Case ◽  
And Performance ◽  
On Chip

To address the performance bottleneck in metal-based interconnects, hybrid optical network-on-chip (HONoC) has emerged as a new alternative. However, as the size of the HONoC grows, insertion loss and crosstalk noise increase, leading to excessive laser source output power and performance degradation. Therefore, we propose a low-power scalable HONoC architecture by incorporating semiconductor optical amplifiers (SOAs). An SOA placement algorithm is developed considering insertion loss and crosstalk noise. Furthermore, we establish a worst-case crosstalk noise model of SOA-enabled HONoC and induce optimized SOA gains with respect to power consumption and performance, respectively. Extensive simulations for worst-case signal-to-noise ratio (SNR) and power consumption are conducted under various traffic patterns and different network sizes. Simulation results show that the proposed SOA-enabled HONoC architecture and the associated algorithm help sustain the performance as network size increases without additional laser source power.

scholarly journals Network-On-Chip Topology Generation and Analysis For Transaction-Based Systems-on-Chip

2021 ◽  
Author(s):  
Victor. Dumitriu
Keyword(s):  
Design Method ◽  
Prediction Method ◽  
Network On Chip ◽  
Network Resources ◽  
Case Scenario ◽  
Worst Case ◽  
Networks On Chip ◽  
Analysis And Design ◽  
Systems On Chip ◽  
On Chip

The Network-on-Chip concept is emerging as a promising new method of addressing the communication requirements of complex Systems-on-Chip. However, network design at this level must take into consideration the specific communication protocols of on-chip components. This thesis presents a topology analysis and design method for networks-on-chip based on the transaction-oriented protocols common to on-chip systems. The generated topologies target the latency of critical links in the system, while the analysis method can predict the degree of contention in a system prior to the simulation phase. The proposed topologies are tested using various applications, including and MPEG4 Decoder, and are found to perform the same or better than regular topologies, while using less network resources. The contention prediction method is found to be accurate to within 27% in the worst case scenario.

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