scholarly journals Design of A Parallel Decoding Method for LDPC Code Generated via Primitive Polynomial

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 425
Author(s):  
Zhe Zhang ◽  
Liang Zhou ◽  
Zhi Heng Zhou

An effective way of improving decoding performance of an LDPC code is to extend the single-decoder decoding method to a parallel decoding method with multiple sub-decoders. To this end, this paper proposes a parallel decoding method for the LDPC codes constructed by m-sequence. In this method, the sub-decoders have two types. The first one contains only one decoding module using the original parity-check constraints to implement a belief propagation (BP) algorithm. The second one consists of a pre-decode module and a decoding module. The parity-check matrices for pre-decode modules are generated by the parity-check constraints of the sub-sequences sampled from an m-sequence. Then, the number of iterations of the BP process in each pre-decode module is set as half of the girth of the parity-check matrix, resulting in the elimination of the impact of short cycles. Using maximum a posterior (MAP), the least metric selector (LMS) finally picks out a codeword from the outputs of sub-decoders. Our simulation results show that the performance gain of the proposed parallel decoding method with five sub-decoders is about 0.4 dB, compared to the single-decoder decoding method at the bit error rate (BER) of 10−5.

2014 ◽  
Vol 909 ◽  
pp. 338-341 ◽  
Author(s):  
Sekson Timakul ◽  
Somsak Choomchuay

In LDPC code, the structure of code's parity check matrix plays the crucial role in code performance. In this paper proposes the preliminary investigation of a designed parity check matrix from Tanner. We modify this technique in to non binary LDPC structure and decoding with FFT-SPA. We take into high code rate application more than 0.8. The result has shown that in bit error rate (BER) compare between non-binary LDPC and binary LDPC. In our results, the performance of non binary LDPC has better than binary LDPC.


2008 ◽  
Vol 44 (11) ◽  
pp. 3773-3776 ◽  
Author(s):  
Y. Nakamura ◽  
M. Nishimura ◽  
Y. Okamoto ◽  
H. Osawa ◽  
H. Muraoka

2021 ◽  
Vol 4 (9(112)) ◽  
pp. 46-53
Author(s):  
Viktor Durcek ◽  
Michal Kuba ◽  
Milan Dado

This paper investigates the construction of random-structure LDPC (low-density parity-check) codes using Progressive Edge-Growth (PEG) algorithm and two proposed algorithms for removing short cycles (CB1 and CB2 algorithm; CB stands for Cycle Break). Progressive Edge-Growth is an algorithm for computer-based design of random-structure LDPC codes, the role of which is to generate a Tanner graph (a bipartite graph, which represents a parity-check matrix of an error-correcting channel code) with as few short cycles as possible. Short cycles, especially the shortest ones with a length of 4 edges, in Tanner graphs of LDPC codes can degrade the performance of their decoding algorithm, because after certain number of decoding iterations, the information sent through its edges is no longer independent. The main contribution of this paper is the unique approach to the process of removing short cycles in the form of CB2 algorithm, which erases edges from the code's parity-check matrix without decreasing the minimum Hamming distance of the code. The two cycle-removing algorithms can be used to improve the error-correcting performance of PEG-generated (or any other) LDPC codes and achieved results are provided. All these algorithms were used to create a PEG LDPC code which rivals the best-known PEG-generated LDPC code with similar parameters provided by one of the founders of LDPC codes. The methods for generating the mentioned error-correcting codes are described along with simulations which compare the error-correcting performance of the original codes generated by the PEG algorithm, the PEG codes processed by either CB1 or CB2 algorithm and also external PEG code published by one of the founders of LDPC codes


2014 ◽  
Vol 4 (1) ◽  
pp. 591-595 ◽  
Author(s):  
L. Jordanova ◽  
L. Laskov ◽  
D. Dobrev

This article presents the results of a study on the noise immunity of DVB channels when higher-order M-ary APSK modulation schemes and concatenated BCH-LDPC codes are used. Dependencies to determine the probability at the decoder output are given taking into consideration the BCH and LDPC code parameters and the error probability in the communication channel. The influence of the BCH packets length, the BCH code rate, the number of maximum iteration and the parameters of LDPC parity-check matrix on the code efficiency is analyzed. Research of the influence of the concatenated LDPC-BCH code parameters on the radio channel noise immunity is conducted and dependencies to determine the required CNR at the input of the satellite receiver are given.


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