scholarly journals An Efficient Dual-Channel Data Storage and Access Method for Spaceborne Synthetic Aperture Radar Real-Time Processing

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 662
Author(s):  
Guoqing Wang ◽  
He Chen ◽  
Yizhuang Xie
Keyword(s):  
Synthetic Aperture Radar ◽  
Real Time ◽  
Data Storage ◽  
Hardware Architecture ◽  
Synthetic Aperture ◽  
Access Method ◽  
Real Time Processing ◽  
Time Processing ◽  
Dual Channel ◽  
Data Controller

With the development of remote sensing technology and very large-scale integrated circuit (VLSI) technology, the real-time processing of spaceborne Synthetic Aperture Radar (SAR) has greatly improved the ability of Earth observation. However, the characteristics of external memory have led to matrix transposition becoming a technical bottleneck that limits the real-time performance of the SAR imaging system. In order to solve this problem, this paper combines the optimized data mapping method and reasonable hardware architecture to implement a data controller based on the Field-Programmable Gate Array (FPGA). First of all, this paper proposes an optimized dual-channel data storage and access method, so that the two-dimensional data access efficiency can be improved. Then, a hardware architecture is designed with register manager, simplified address generator and dual-channel Double-Data-Rate Three Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) access mode. Finally, the proposed data controller is implemented on the Xilinx XC7VX690T FPGA chip. The experimental results show that the reading efficiency of the data controller proposed is 80% both in the range direction and azimuth direction, and the writing efficiency is 66% both in the range direction and azimuth direction. The results of a comparison with the recent implementations show that the proposed data controller has a higher data bandwidth, is more flexible in its design, and is suitable for use in spaceborne scenarios.

A real-time processing system for dual-channel six-degree-of-freedom grating ruler based on FPGA

2021 ◽  
Author(s):  
Ningning Shi ◽  
Shengtong Wang ◽  
Gaopeng Xue ◽  
Mengfang Liu ◽  
Yaodong Han ◽  
...  
Keyword(s):  
Real Time ◽  
Processing System ◽  
Degree Of Freedom ◽  
Real Time Processing ◽  
Time Processing ◽  
Dual Channel ◽  
Six Degree Of Freedom

scholarly journals FPGA Implementation of the Range-Doppler Algorithm for Real-Time Synthetic Aperture Radar Imaging

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2133
Author(s):  
Yeongung Choi ◽  
Dongmin Jeong ◽  
Myeongjin Lee ◽  
Wookyung Lee ◽  
Yunho Jung
Keyword(s):  
Synthetic Aperture Radar ◽  
Real Time ◽  
Execution Time ◽  
Synthetic Aperture ◽  
Processing Unit ◽  
Path Delay ◽  
Real Time Processing ◽  
Range Cell ◽  
Range Cell Migration ◽  
Aperture Radar

In this paper, we propose a range-Doppler algorithm (RDA)-based synthetic aperture radar (SAR) processor for real-time SAR imaging and present FPGA-based implementation results. The processing steps for the RDA include range compression, range cell migration correction (RCMC), and azimuth compression. A matched filtering unit (MFU) and an RCMC processing unit (RPU) are required for real-time processing. Therefore, the proposed RDA-based SAR processor contains an MFU that uses the mixed-radix multi-path delay commutator (MRMDC) FFT and an RPU. The MFU reduces the memory requirements by applying a decimation-in-frequency (DIF) FFT and decimation-in-time (DIT) IFFT. The RPU provides a variable tap size and variable interpolation kernel. In addition, the MFU and RPU are designed to enable parallel processing of four 32-bit which are transferred via a 128-bit AXI bus. The proposed RDA-based SAR processor was designed using Verilog-HDL and implemented in a Xilinx UltraScale+ MPSoC FPGA device. After comparing the execution time taken by the proposed SAR processor with that taken by an ARM cortex-A53 microprocessor, we observed a 85-fold speedup for a 2048 × 2048 pixel image. A performance evaluation based on related studies indicated that the proposed processor achieved an execution time that was approximately 6.5 times less than those of previous FPGA implementations of RDA processors.

scholarly journals Area & Power Efficient VLSI Architecture of Mode Decision in Integer Motion Estimation for HEVC Video Coding Standard

2019 ◽  
Vol 9 (4) ◽  
pp. 2469
Author(s):  
EL Ansari Abdessamad ◽  
Nejmeddine Bahri ◽  
Anass Mansouri ◽  
Nouri Masmoud ◽  
Ahaitouf Ali
Keyword(s):  
Motion Estimation ◽  
Real Time ◽  
Vlsi Architecture ◽  
Hardware Architecture ◽  
Video Encoding ◽  
Mode Decision ◽  
Decision Algorithm ◽  
Real Time Processing ◽  
Time Processing ◽  
Block Sizes

<span lang="EN-US">In this paper, we propose a new parallel hardware architecture for the mode decision algorithm, that it is based on the Sum Absolute of the Difference (SAD) for compute the motion estimation, which is the most critical algorithm in the recent video encoding standard HEVC. In fact, this standard introduced new large variable block sizes for the motion estimation algorithm and therefore the SAD requires a more reduced execution time in order to achieve the real time processing even for the ultra-high resolution sequences. The proposed accelerator executes the SAD algorithm in a parallel way for all sub-block prediction units (PUs) and coding unit (CU) whatever their sizes, which turns in a huge improvements in the performances, given that all the block sizes, PUs in each CU, are supported and processed in the same time. The Xilinx Artix-7 (Zynq-7000) FPGA is used for the prototyping and the synthesis of the proposed accelerator. The mode decision for motion estimation scheme is implemented with 32K LUTs, 50K registers and 108Kb BRAMs. The implementation results show that our hardware architecture can achieve 30 frames per second of the 4K (3840 × 2160) resolutions in real time processing at 115.15MHz.</span>

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