scholarly journals Efficient Iterative Process based on an Improved Genetic Algorithm for Decoupling Capacitor Placement at Board Level

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1219 ◽  
Author(s):  
de Paulis ◽  
Cecchetti ◽  
Olivieri ◽  
Piersanti ◽  
Orlandi ◽  
...  
Keyword(s):  
Genetic Algorithm ◽  
Frequency Spectrum ◽  
Input Impedance ◽  
Iterative Process ◽  
Power Delivery ◽  
Improved Genetic Algorithm ◽  
Decoupling Capacitors ◽  
Power Delivery Network ◽  
Capacitor Placement ◽  
Board Level

To reduce the noise created by a power delivery network, the number, the value of decoupling capacitors and their arrangement on the board are critical to reaching this goal. This work deals with specific improvements, implemented on a genetic algorithm, which used for the optimization of the decoupling capacitors in order to obtain the frequency spectrum of the input impedance in different positions on the network, below previously defined values. Measurements are performed on a specifically manufactured board in order to validate the effectiveness of the proposed algorithm and the optimization results obtained for a specific example board.

scholarly journals Decoupling Capacitors Placement at Board Level Adopting a Nature-Inspired Algorithm

Electronics ◽  
2019 ◽  
Vol 8 (7) ◽  
pp. 737 ◽  
Author(s):  
Stefano Piersanti ◽  
Riccardo Cecchetti ◽  
Carlo Olivieri ◽  
Francesco de Paulis ◽  
Antonio Orlandi ◽  
...  
Keyword(s):  
Objective Function ◽  
Input Impedance ◽  
Numerical Results ◽  
Power Delivery ◽  
Decoupling Capacitors ◽  
Power Delivery Networks ◽  
Power Delivery Network ◽  
Nature Inspired Algorithm ◽  
Delivery Networks ◽  
Board Level

Decoupling capacitors are fundamental keys for the reduction of transient noise in power delivery networks; their arrangement and values are crucial for reaching this goal. This work deals with the optimization of the decoupling capacitors of a power delivery network by using a nature-inspired algorithm. In particular, the capacitance value and the location of three decoupling capacitors are optimized in order to obtain an input impedance below a specific mask, by using a nature-inspired algorithm, the genetic one, in combination with two electromagnetic solvers used to compute the objective function. An experimental board is designed and manufactured; measurements are performed to validate the numerical results.

scholarly journals Effective PCB Decoupling Optimization by Combining an Iterative Genetic Algorithm and Machine Learning

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1243 ◽  
Author(s):  
Riccardo Cecchetti ◽  
Francesco de Paulis ◽  
Carlo Olivieri ◽  
Antonio Orlandi ◽  
Markus Buecker
Keyword(s):  
Genetic Algorithm ◽  
Power Delivery ◽  
Computational Time ◽  
Test Cases ◽  
Experimental Measurements ◽  
New Approach ◽  
Power Delivery Network ◽  
Capacitor Placement ◽  
Minimum Number ◽  
Artificial Neural Network Ann

An iterative optimization for decoupling capacitor placement on a power delivery network (PDN) is presented based on Genetic Algorithm (GA) and Artificial Neural Network (ANN). The ANN is first trained by an appropriate set of results obtained by a commercial simulator. Once the ANN is ready, it is used within an iterative GA process to place a minimum number of decoupling capacitors for minimizing the differences between the input impedance at one or more location, and the required target impedance. The combined GA–ANN process is shown to effectively provide results consistent with those obtained by a longer optimization based on commercial simulators. With the new approach the accuracy of the results remains at the same level, but the computational time is reduced by at least 30 times. Two test cases have been considered for validating the proposed approach, with the second one also being compared by experimental measurements.

A New Testability Optimization Allocation Approach

2013 ◽  
Vol 328 ◽  
pp. 444-449 ◽  
Author(s):  
Gang Liu ◽  
Fang Li
Keyword(s):  
Genetic Algorithm ◽  
Genetic Algorithms ◽  
Iterative Process ◽  
Resource Constraints ◽  
Optimal Solution ◽  
Improved Genetic Algorithm ◽  
Numerical Example ◽  
Set Up ◽  
Optimization Allocation ◽  
Allocation Approach

This paper describes a methodology based on improved genetic algorithms (GA) and experiments plan to optimize the testability allocation. Test resources were reasonably configured for testability optimization allocation, in order to meet the testability allocation requirements and resource constraints. The optimal solution was not easy to solve of general genetic algorithm, and the initial parameter value was not easy to set up and other defects. So in order to more efficiently test and optimize the allocation, migration technology was introduced in the traditional genetic algorithm to optimize the iterative process, and initial parameters of algorithm could be adjusted by using AHP approach, consequently testability optimization allocation approach based on improved genetic algorithm was proposed. A numerical example is used to assess the method. and the examples show that this approach can quickly and efficiently to seek the optimal solution of testability optimization allocation problem.

Research of Chip Placement and Routing Algorithms for Board-Level Photoelectric Interconnection

2014 ◽  
Vol 556-562 ◽  
pp. 1577-1579
Author(s):  
Jian Liu ◽  
Zhao Hua Wu
Keyword(s):  
Genetic Algorithm ◽  
Genetic Algorithms ◽  
Routing Algorithms ◽  
Optimal Placement ◽  
Improved Method ◽  
Improved Genetic Algorithm ◽  
C Language ◽  
Placement And Routing ◽  
Board Level ◽  
Improved Algorithm

This document improved genetic algorithm and Intelligent discern points algorithmin chip placement and routing for Board-level photoelectric interconnection, by comparisonofthe algorithm results to verify the effectiveness and practicality of the improved algorithm. First introduced the features of chip placement and routing for Board-level Photoelectric Interconnection. Then describes the improved method of genetic algorithms and intelligent discern points algorithms. Finally, implement algorithm by C language on VC6.0++ platform, while the data import MATLAB to displays the optimal placement and routing results. The results show that the effectiveness of improved algorithm, which has a guiding significance for the chip placement and routing.

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