FPGA verification technology based on Synopsys VMM

Journal of Computer Applications ◽

10.3724/sp.j.1087.2009.02527 ◽

2009 ◽

Vol 29 (9) ◽

pp. 2527-2529

Author(s):

Xin-xin Lü ◽

Shu-fen LIU

Keyword(s):

Fpga Verification

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The Design and FPGA Verification of a General Structure, Area-optimized Interpolation Filter Used in /spl Delta/-/spl Sigma/ DAC

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings ◽

10.1109/icsict.2006.306632 ◽

2006 ◽

Author(s):

Xiaowei Huang ◽

Yan Han ◽

Lei Chen

Keyword(s):

General Structure ◽

Interpolation Filter ◽

Fpga Verification

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Implementation of Data Automation System using SDK's Memory Map for FPGA Verification

The Journal of Korean Institute of Information Technology ◽

10.14801/jkiit.2020.18.10.133 ◽

2020 ◽

Vol 18 (10) ◽

pp. 133-138

Author(s):

Sangwook Park ◽

Bongsoon Kang

Keyword(s):

Automation System ◽

Fpga Verification

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Digital background calibration for pipelined ADC and implementation of Full FPGA verification platform

2012 5th International Congress on Image and Signal Processing ◽

10.1109/cisp.2012.6469847 ◽

2012 ◽

Author(s):

Yi-Long Zhu ◽

Yong-Sheng Yin ◽

Ming Wang ◽

Wei Ni

Keyword(s):

Pipelined Adc ◽

Background Calibration ◽

Digital Background Calibration ◽

Fpga Verification

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The FPGA verification of USB to RS-232 bridge controller

International Conference on Automatic Control and Artificial Intelligence (ACAI 2012) ◽

10.1049/cp.2012.1418 ◽

2012 ◽

Author(s):

Sun Fengdong ◽

Zhao Hongwei ◽

Liang Jianguo ◽

Hou Shufan

Keyword(s):

Fpga Verification

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FPGA Verification Module

Proceedings of the E2LP 2014 Workshop ◽

10.15439/2014f673 ◽

2014 ◽

Author(s):

Ivan Aleksi ◽

Željko Hocenski

Keyword(s):

Fpga Verification

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Three IP Soft-Core Designs of ADC and FPGA Verification

Communications in Computer and Information Science - Communications and Information Processing ◽

10.1007/978-3-642-31968-6_15 ◽

2012 ◽

pp. 123-130

Author(s):

JiangFeng Sun ◽

Feng Chen

Keyword(s):

Soft Core ◽

Fpga Verification

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Volatile Register Handling for FPGA Verification Based on SVAs Incorporated into UVM Environments

2019 IEEE Aerospace Conference ◽

10.1109/aero.2019.8742109 ◽

2019 ◽

Author(s):

Kai Borchers ◽

Sergio Montenegro ◽

Frank Dannemann

Keyword(s):

Fpga Verification

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Design and FPGA verification of a quasi-cyclic LDPC code for optical communication systems

2016 8th IEEE Latin-American Conference on Communications (LATINCOM) ◽

10.1109/latincom.2016.7811566 ◽

2016 ◽

Author(s):

Genaro Bergero ◽

Damian A. Morero ◽

Ariel L. Pola ◽

Mario A. Castrillon ◽

Mario R. Hueda

Keyword(s):

Optical Communication ◽

Communication Systems ◽

Ldpc Code ◽

Fpga Verification ◽

Optical Communication Systems

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Design and FPGA Verification of Custom-Shaped Chaotic Attractors Using Rotation, Offset Boosting and Amplitude Control

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2021.3082271 ◽

2021 ◽

pp. 1-1

Author(s):

Wafaa S. Sayed ◽

Merna Roshdy ◽

Lobna A. Said ◽

Ahmed G. Radwan

Keyword(s):

Chaotic Attractors ◽

Amplitude Control ◽

Offset Boosting ◽

Fpga Verification

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FPGA Verification of a Single QC-LDPC Code for 100 Gb/s Optical Systems without Error Floor down to BER of 10−15

Optical Fiber Communication Conference/National Fiber Optic Engineers Conference 2011 ◽

10.1364/ofc.2011.otun2 ◽

2011 ◽

Author(s):

Deyuan Chang ◽

Fan Yu ◽

Zhiyu Xiao ◽

Yang Li ◽

Nebojsa Stojanovic ◽

...

Keyword(s):

Ldpc Code ◽

Optical Systems ◽

Error Floor ◽

Fpga Verification

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