Digital background calibration for pipelined ADC and implementation of Full FPGA verification platform

Fpga Verification

Digital Background Calibration for a 14-bit 100-MS/s Pipelined ADC Using Signal-Dependent Dithering

IEICE Transactions on Electronics ◽

10.1587/transele.e97.c.207 ◽

2014 ◽

Vol E97.C (3) ◽

pp. 207-214

Author(s):

Zhao-xin XIONG ◽

Min CAI ◽

Xiao-Yong HE ◽

Yun YANG

Keyword(s):

Pipelined Adc ◽

Background Calibration ◽

12 bit 3.072 GS/s 32‐way time‐interleaved pipelined ADC with digital background calibration for wideband fully digital receiver application in 65 nm complementary metal–oxide–semiconductor

IET Circuits Devices & Systems ◽

10.1049/iet-cds.2019.0069 ◽

2020 ◽

Vol 14 (2) ◽

pp. 182-191

Author(s):

Waleed Hussain Siddiqui ◽

Goang Seong Choi

Keyword(s):

Metal Oxide ◽

Complementary Metal Oxide Semiconductor ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Pipelined Adc ◽

Digital Receiver ◽

Background Calibration ◽

Time Interleaved

2014 9th International Symposium on Communication Systems, Networks & Digital Sign (CSNDSP) ◽

An adaptive digital background calibration technique using variable step size LMS for pipelined ADC

10.1109/csndsp.2014.6923943 ◽

2014 ◽

Author(s):

Nahla T. Abou-El-Kheir ◽

Mohmed Abbas ◽

Mohamed Essam Khedr

Keyword(s):

Variable Step Size ◽

Pipelined Adc ◽

Background Calibration ◽

Calibration Technique ◽

Step Size ◽

Variable Step

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) ◽

A new digital background calibration technique for pipelined ADC

10.1109/iscas.2004.1328117 ◽

2004 ◽

Cited By ~ 1

Author(s):

K. El-Sankary ◽

M. Sawan

Keyword(s):

Pipelined Adc ◽

Background Calibration ◽

Calibration Technique ◽

2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES) ◽

A fast power efficient equalization-based digital background calibration technique for pipelined ADC

10.1109/mixdes.2014.6872166 ◽

2014 ◽

Author(s):

Nahla T. Abou-El-Kheir ◽

Mohammed Essam Khedr ◽

Mohamed Abbas

Keyword(s):

Pipelined Adc ◽

Background Calibration ◽

Calibration Technique ◽

Power Efficient ◽

Fast Power

A 12-bit 20-MS/s pipelined ADC with nested digital background calibration

Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003. ◽

10.1109/cicc.2003.1249429 ◽

2004 ◽

Cited By ~ 26

Author(s):

X. Wang ◽

P.J. Hurst ◽

S.H. Lewis

Keyword(s):

Pipelined Adc ◽

Background Calibration ◽

A 2.9-mW 11-b 20-MS/s pipelined ADC with dual-mode-based digital background calibration

2012 Proceedings of the ESSCIRC (ESSCIRC) ◽

10.1109/esscirc.2012.6341337 ◽

2012 ◽

Cited By ~ 9

Author(s):

Nan Sun ◽

Hae-Seung Lee ◽

Donhee Ham

Keyword(s):

Pipelined Adc ◽

Background Calibration ◽

Dual Mode ◽

2010 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) ◽

Modeling of digital background calibration with signal-dependent dithering for a 14-bit, 100-MS/s pipelined ADC

10.1109/primeasia.2010.5604947 ◽

2010 ◽

Author(s):

Kexu Sun ◽

Xuan Wang ◽

Lenian He

Keyword(s):

Pipelined Adc ◽

Background Calibration ◽

2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC) ◽

Blind-LMS based digital background calibration for a 14-Bit 200-MS/s pipelined ADC

10.1109/vlsi-soc.2013.6673307 ◽

2013 ◽

Author(s):

Yajuan He ◽

Bo Chen ◽

Qiang Li

Keyword(s):

Pipelined Adc ◽

Background Calibration ◽

Digital background calibration of a 0.4-pJ/step 10-bit pipelined ADC without PN generator in 90-nm digital CMOS

2008 IEEE Asian Solid-State Circuits Conference ◽

10.1109/asscc.2008.4708727 ◽

2008 ◽

Cited By ~ 6

Author(s):

Mohammad Taherzadeh-Sani ◽

Anas A. Hamoui

Keyword(s):

Pipelined Adc ◽

Background Calibration ◽

Digital Cmos ◽