Low-Power Data Cache Architecture and Microarchitecture-level Management Policy for Multimedia Application

The KIPS Transactions PartA ◽

10.3745/kipsta.2006.13a.3.191 ◽

2006 ◽

Vol 13A (3) ◽

pp. 191-198

Author(s):

Hoon-Mo Yang ◽

Cheong-Gil Kim ◽

Gi-Ho Park ◽

Shin-Dug Kim

Keyword(s):

Low Power ◽

Multimedia Application ◽

Management Policy ◽

Cache Architecture

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Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications

Advances in Computer Systems Architecture - Lecture Notes in Computer Science ◽

10.1007/11859802_60 ◽

2006 ◽

pp. 574-580

Author(s):

Hoon-Mo Yang ◽

Gi-Ho Park ◽

Shin-Dug Kim

Keyword(s):

Low Power ◽

Multimedia Applications ◽

Cache Architecture

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Lightweight set buffer: low power data cache for multimedia application

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03. ◽

10.1109/lpe.2003.1231875 ◽

2003 ◽

Author(s):

Jun Yang ◽

Jia Yu ◽

Youtao Zhang

Keyword(s):

Low Power ◽

Multimedia Application ◽

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Design of low power L2 cache architecture using partial way tag information

2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE) ◽

10.1109/icgccee.2014.6922292 ◽

2014 ◽

Author(s):

A. Divya Jebaseeli ◽

M. Kiruba

Keyword(s):

Low Power ◽

Cache Architecture ◽

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A Variable Bitline Data Cache for low power design

2010 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) ◽

10.1109/primeasia.2010.5604932 ◽

2010 ◽

Author(s):

Jiongyao Ye ◽

Takahiro Watanabe

Keyword(s):

Low Power ◽

Low Power Design ◽

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Demand-Aware NVM Capacity Management Policy for Hybrid Cache Architecture

The Computer Journal ◽

10.1093/comjnl/bxv103 ◽

2015 ◽

Vol 59 (5) ◽

pp. 685-700

Author(s):

Ju-Hee Choi ◽

Gi-Ho Park

Keyword(s):

Capacity Management ◽

Management Policy ◽

Cache Architecture ◽

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A low power unified cache architecture providing power and performance flexibility

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514) ◽

10.1109/lpe.2000.876794 ◽

2002 ◽

Author(s):

A. Malik ◽

B. Moyer ◽

D. Cermak

Keyword(s):

Low Power ◽

Cache Architecture ◽

And Performance

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A low-power phase change memory based hybrid cache architecture

Proceedings of the 18th ACM Great Lakes symposium on VLSI - GLSVLSI '08 ◽

10.1145/1366110.1366204 ◽

2008 ◽

Author(s):

Prasanth Mangalagiri ◽

Karthik Sarpatwari ◽

Aditya Yanamandra ◽

VijayKrishnan Narayanan ◽

Yuan Xie ◽

...

Keyword(s):

Low Power ◽

Phase Change ◽

Phase Change Memory ◽

Cache Architecture ◽

Hybrid Cache ◽

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A New Hierarchical Data Cache Architecture for iSCSI Storage Server

IEEE Transactions on Computers ◽

10.1109/tc.2008.166 ◽

2009 ◽

Vol 58 (4) ◽

pp. 433-447 ◽

Author(s):

Jun Wang ◽

Xiaoyu Yao ◽

Christopher Mitchell ◽

Peng Gu

Keyword(s):

Hierarchical Data ◽

Storage Server ◽

Cache Architecture

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Toward Effective NIC Caching: A Hierarchical Data Cache Architecture for iSCSI Storage Servers

2005 International Conference on Parallel Processing (ICPP'05) ◽

10.1109/icpp.2005.76 ◽

2005 ◽

Author(s):

Xiaoyu Yao ◽

Jun Wang

Keyword(s):

Hierarchical Data ◽

Cache Architecture ◽

Storage Servers

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A compiler-controlled instruction cache architecture for an embedded low power microprocessor

The Fifth International Conference on Computer and Information Technology (CIT'05) ◽

10.1109/cit.2005.3 ◽

2005 ◽

Author(s):

Xiaoping Zhu ◽

T.T. Tay

Keyword(s):

Low Power ◽

Instruction Cache ◽

Cache Architecture

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