Design of low power L2 cache architecture using partial way tag information

2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE) ◽

10.1109/icgccee.2014.6922292 ◽

2014 ◽

Author(s):

A. Divya Jebaseeli ◽

M. Kiruba

Keyword(s):

Low Power ◽

Cache Architecture ◽

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Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications

Advances in Computer Systems Architecture - Lecture Notes in Computer Science ◽

10.1007/11859802_60 ◽

2006 ◽

pp. 574-580

Author(s):

Hoon-Mo Yang ◽

Gi-Ho Park ◽

Shin-Dug Kim

Keyword(s):

Low Power ◽

Multimedia Applications ◽

Cache Architecture

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A low power unified cache architecture providing power and performance flexibility

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514) ◽

10.1109/lpe.2000.876794 ◽

2002 ◽

Author(s):

A. Malik ◽

B. Moyer ◽

D. Cermak

Keyword(s):

Low Power ◽

Cache Architecture ◽

And Performance

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A low-power phase change memory based hybrid cache architecture

Proceedings of the 18th ACM Great Lakes symposium on VLSI - GLSVLSI '08 ◽

10.1145/1366110.1366204 ◽

2008 ◽

Author(s):

Prasanth Mangalagiri ◽

Karthik Sarpatwari ◽

Aditya Yanamandra ◽

VijayKrishnan Narayanan ◽

Yuan Xie ◽

...

Keyword(s):

Low Power ◽

Phase Change ◽

Phase Change Memory ◽

Cache Architecture ◽

Hybrid Cache ◽

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A compiler-controlled instruction cache architecture for an embedded low power microprocessor

The Fifth International Conference on Computer and Information Technology (CIT'05) ◽

10.1109/cit.2005.3 ◽

2005 ◽

Author(s):

Xiaoping Zhu ◽

T.T. Tay

Keyword(s):

Low Power ◽

Instruction Cache ◽

Cache Architecture

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Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints

Power-Aware Computer Systems - Lecture Notes in Computer Science ◽

10.1007/3-540-36612-1_2 ◽

2003 ◽

pp. 18-32

Author(s):

Koji Inoue ◽

Vasily Moshnyaga ◽

Kazuaki Murakami

Keyword(s):

Low Power ◽

Instruction Cache ◽

Cache Architecture

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Low-Power Data Cache Architecture and Microarchitecture-level Management Policy for Multimedia Application

The KIPS Transactions PartA ◽

10.3745/kipsta.2006.13a.3.191 ◽

2006 ◽

Vol 13A (3) ◽

pp. 191-198

Author(s):

Hoon-Mo Yang ◽

Cheong-Gil Kim ◽

Gi-Ho Park ◽

Shin-Dug Kim

Keyword(s):

Low Power ◽

Multimedia Application ◽

Management Policy ◽

Cache Architecture

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A leakage-aware L2 cache management technique for producer–consumer sharing in low-power chip multiprocessors

Journal of Parallel and Distributed Computing ◽

10.1016/j.jpdc.2011.08.006 ◽

2011 ◽

Vol 71 (12) ◽

pp. 1545-1557 ◽

Author(s):

Hyunhee Kim ◽

Jihong Kim

Keyword(s):

Low Power ◽

Chip Multiprocessors ◽

Management Technique ◽

Cache Management ◽

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DHL‐cache: dynamic per history length adjustment for low‐power L2 cache

Electronics Letters ◽

10.1049/el.2016.1465 ◽

2016 ◽

Vol 52 (15) ◽

pp. 1297-1298

Author(s):

H.W. Joo ◽

E.Y. Chung

Keyword(s):

Low Power ◽

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Low power data-aware STT-RAM based hybrid cache architecture

2016 17th International Symposium on Quality Electronic Design (ISQED) ◽

10.1109/isqed.2016.7479181 ◽

2016 ◽

Author(s):

Mohsen Imani ◽

Shruti Patil ◽

Tajana Rosing

Keyword(s):

Low Power ◽

Cache Architecture ◽

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3D implemented SRAM/DRAM hybrid cache architecture for high-performance and low power consumption

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS) ◽

10.1109/mwscas.2011.6026484 ◽

2011 ◽

Author(s):

Koji Inoue ◽

Shinya Hashiguchi ◽

Shinya Ueno ◽

Naoto Fukumoto ◽

Kazuaki Murakami

Keyword(s):

Power Consumption ◽

Low Power ◽

High Performance ◽

Low Power Consumption ◽

Cache Architecture ◽

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