Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications

Advances in Computer Systems Architecture - Lecture Notes in Computer Science ◽

10.1007/11859802_60 ◽

2006 ◽

pp. 574-580

Author(s):

Hoon-Mo Yang ◽

Gi-Ho Park ◽

Shin-Dug Kim

Keyword(s):

Low Power ◽

Multimedia Applications ◽

Cache Architecture

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Low-Power Data Cache Architecture and Microarchitecture-level Management Policy for Multimedia Application

The KIPS Transactions PartA ◽

10.3745/kipsta.2006.13a.3.191 ◽

2006 ◽

Vol 13A (3) ◽

pp. 191-198

Author(s):

Hoon-Mo Yang ◽

Cheong-Gil Kim ◽

Gi-Ho Park ◽

Shin-Dug Kim

Keyword(s):

Low Power ◽

Multimedia Application ◽

Management Policy ◽

Cache Architecture

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Low-Power Video Decoding on Variable Voltage Processor for Mobile Multimedia Applications

ETRI Journal ◽

10.4218/etrij.05.0905.0002 ◽

2005 ◽

Vol 27 (5) ◽

pp. 504-510 ◽

Author(s):

Seongsoo Lee

Keyword(s):

Low Power ◽

Multimedia Applications ◽

Mobile Multimedia ◽

Video Decoding ◽

Variable Voltage ◽

Variable Voltage Processor

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Design of low power L2 cache architecture using partial way tag information

2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE) ◽

10.1109/icgccee.2014.6922292 ◽

2014 ◽

Author(s):

A. Divya Jebaseeli ◽

M. Kiruba

Keyword(s):

Low Power ◽

Cache Architecture ◽

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A low power chipset for portable multimedia applications

Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94 ◽

10.1109/isscc.1994.344718 ◽

2002 ◽

Author(s):

A. Chandrakasan ◽

A. Burstein ◽

R.W. Brodersen

Keyword(s):

Low Power ◽

Multimedia Applications

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Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. ◽

10.1109/lpe.2005.195507 ◽

2005 ◽

Author(s):

M. Lanuzza ◽

M. Margala ◽

P. Corsonello

Keyword(s):

Low Power ◽

Cost Effective ◽

Multimedia Applications

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A Methodology for Low-Power Approximate Embedded SRAM Within Multimedia Applications

2018 31st IEEE International System-on-Chip Conference (SOCC) ◽

10.1109/socc.2018.8618492 ◽

2018 ◽

Author(s):

Samira Ataei ◽

James E. Stine

Keyword(s):

Low Power ◽

Multimedia Applications ◽

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A Variable Bitline Data Cache for low power design

2010 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) ◽

10.1109/primeasia.2010.5604932 ◽

2010 ◽

Author(s):

Jiongyao Ye ◽

Takahiro Watanabe

Keyword(s):

Low Power ◽

Low Power Design ◽

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Ultra-Thin (4nm) Gate-All-Around CMOS devices with High-k/Metal for Low Power Multimedia Applications

10.7567/ssdm.2010.c-5-2 ◽

2010 ◽

Author(s):

J. L. Huguenin ◽

S. Monfray ◽

G. Bidal ◽

S. Denorme ◽

P. Perreau ◽

...

Keyword(s):

Low Power ◽

Multimedia Applications ◽

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A low power unified cache architecture providing power and performance flexibility

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514) ◽

10.1109/lpe.2000.876794 ◽

2002 ◽

Author(s):

A. Malik ◽

B. Moyer ◽

D. Cermak

Keyword(s):

Low Power ◽

Cache Architecture ◽

And Performance

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A low-power phase change memory based hybrid cache architecture

Proceedings of the 18th ACM Great Lakes symposium on VLSI - GLSVLSI '08 ◽

10.1145/1366110.1366204 ◽

2008 ◽

Author(s):

Prasanth Mangalagiri ◽

Karthik Sarpatwari ◽

Aditya Yanamandra ◽

VijayKrishnan Narayanan ◽

Yuan Xie ◽

...

Keyword(s):

Low Power ◽

Phase Change ◽

Phase Change Memory ◽

Cache Architecture ◽

Hybrid Cache ◽

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