Caching and Prefetching Policies Using Program Page Reference Patterns on a File System Layer for NAND Flash Memory

2007 ◽  
Vol 14A (4) ◽  
pp. 235-244 ◽  
Author(s):  
Sang-Oh Park ◽  
Kyung-San Kim ◽  
Sung-Jo Kim

2006 ◽  
Vol 2 (3) ◽  
pp. 147-152 ◽  
Author(s):  
Song-Hwa Park ◽  
Tae-Hoon Lee ◽  
Ki-Dong Chung






2012 ◽  
Vol E95.C (5) ◽  
pp. 837-841 ◽  
Author(s):  
Se Hwan PARK ◽  
Yoon KIM ◽  
Wandong KIM ◽  
Joo Yun SEO ◽  
Hyungjin KIM ◽  
...  


2020 ◽  
Vol E103.C (4) ◽  
pp. 171-180
Author(s):  
Yoshiki TAKAI ◽  
Mamoru FUKUCHI ◽  
Chihiro MATSUI ◽  
Reika KINOSHITA ◽  
Ken TAKEUCHI




Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 879
Author(s):  
Ruiquan He ◽  
Haihua Hu ◽  
Chunru Xiong ◽  
Guojun Han

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.



Sign in / Sign up

Export Citation Format

Share Document