Implementation and Evaluation of Skip-Links

2013 ◽  
pp. 181-203
Author(s):  
Simon J. Hollis ◽  
Chris Jackson
Keyword(s):  
Long Range ◽  
Traffic Patterns ◽  
Master Node ◽  
Hop Count ◽  
Core Networks ◽  
Mesh Topology ◽  
Node Network ◽  
On Chip ◽  
Many Core ◽  
Prior Analysis

The Skip-link architecture dynamically reconfigures Network-on-Chip (NoC) topologies in order to reduce the overall switching activity in many-core systems. The proposed architecture allows the creation of long-range Skip-links at runtime to reduce the logical distance between frequently communicating nodes. This offers a number of advantages over existing methods of creating optimised topologies already present in research, such as the Reconfigurable NoC (ReNoC) architecture and static Long-Range Link (LRL) insertion. This architecture monitors traffic behaviour and optimises the mesh topology without prior analysis of communications behaviour, and is thus applicable to all applications. The technique described here does not utilise a master node, and each router acts independently. The architecture is thus scalable to future many-core networks. The authors evaluate the performance using a cycle-accurate simulator with synthetic traffic patterns and compare the results to a mesh architecture, demonstrating logical hop count reductions of 12-17%. Coupled with this, up to a doubling in critical load is observed, and the potential for 10% energy reductions on a 16×16 node network.

Implementation and Evaluation of Skip-Links

2011 ◽  
Vol 2 (3) ◽  
pp. 21-49 ◽  
Author(s):  
Simon J. Hollis ◽  
Chris Jackson
Keyword(s):  
Long Range ◽  
Switching Activity ◽  
Traffic Patterns ◽  
Hop Count ◽  
Core Networks ◽  
Mesh Topology ◽  
Node Network ◽  
On Chip ◽  
Many Core ◽  
Prior Analysis

The Skip-link architecture dynamically reconfigures Network-on-Chip (NoC) topologies in order to reduce the overall switching activity in many-core systems. The proposed architecture allows the creation of long-range Skip-links at runtime to reduce the logical distance between frequently communicating nodes. This offers a number of advantages over existing methods of creating optimised topologies already present in research, such as the Reconfigurable NoC (ReNoC) architecture and static Long-Range Link (LRL) insertion. This architecture monitors traffic behaviour and optimises the mesh topology without prior analysis of communications behaviour, and is thus applicable to all applications. The technique described here does not utilise a master node, and each router acts independently. The architecture is thus scalable to future many-core networks. The authors evaluate the performance using a cycle-accurate simulator with synthetic traffic patterns and compare the results to a mesh architecture, demonstrating logical hop count reductions of 12-17%. Coupled with this, up to a doubling in critical load is observed, and the potential for 10% energy reductions on a 16×16 node network.

scholarly journals Hotspot-aware task-resource co-allocation for heterogeneous many-core networks-on-chip

2018 ◽  
Vol 68 ◽  
pp. 581-602 ◽  
Author(s):  
Md Farhadur Reza ◽  
Dan Zhao ◽  
Hongyi Wu ◽  
Magdy Bayoumi
Keyword(s):  
Networks On Chip ◽  
Core Networks ◽  
On Chip ◽  
Many Core

scholarly journals Evaluation of Over Looped 2d Mesh Topology for Network on Chip

2019 ◽  
Vol 8 (9) ◽  
pp. 502-504
Keyword(s):  
Network On Chip ◽  
The Other ◽  
Hop Count ◽  
Mesh Topology ◽  
Homogeneous Systems ◽  
Outer Corner ◽  
On Chip ◽  
2D Torus ◽  
Opposite Corner ◽  
Structural Arrangements

The arrangements of nodes in the network identifies the complexity of the network. To reduce the complexity, a structural arrangements of nodes has to be taken care. The mesh topology yields attraction than the other traditional topologies. Making the opposite corner nodes to communicate with less hops and avoiding the centre of the networks traffic, Over-Looped 2D Mesh Topology is proposed. For a homogeneous systems the proposed work can be deployed without altering any of the switch component compositions. By making the flits, travel in the outer corner nodes with the help of looping nodes will make the journey from source to destination with less hops. For smaller network below 4x4 the looping is less responsive. For odd or even number of columns and rows the looping can be done. The number of columns and number of rows need not to be equal. The left over nodes will be looped accordingly. The hop count of the Over-Looped 2D Mesh Topology compared to 2D mesh decreases the journey by 25%. The wiring segmentation and the wiring length of the system more than 10 % from 2D mesh and less than 20% from 2D Torus

scholarly journals A Multi-Phase Based Multi-Application Mapping Approach for Many-Core Networks-on-Chip

Micromachines ◽  
2021 ◽  
Vol 12 (6) ◽  
pp. 613
Author(s):  
Fen Ge ◽  
Chenchen Cui ◽  
Fang Zhou ◽  
Ning Wu
Keyword(s):  
Simulated Annealing Algorithm ◽  
Optimal Placement ◽  
Networks On Chip ◽  
Core Networks ◽  
Application Mapping ◽  
Mapping Approach ◽  
On Chip ◽  
The One ◽  
Multi Phase ◽  
Many Core

More and more attention is being paid to the use of massive parallel computing performed on many-core Networks-on-Chip (NoC) in order to accelerate performance. Simultaneously deploying multiple applications on NoC is one feasible way to achieve this. In this paper, we propose a multi-phase-based multi-application mapping approach for NoC design. Our approach began with a rectangle analysis, which offered several potential regions for application. Then we mapped all tasks of the application into these potential regions using a genetic algorithm, and identified the one which exhibited the strongest performance. When the packeted regions for each application were identified, a B*Tree-based simulated annealing algorithm was used to generate the optimal placement for the multi-application mapping regions. The experiment results show that the proposed approach can achieve a considerable reduction in network power consumption (up to 23.45%) and latency (up to 24.42%) for a given set of applications.

Cluster Based Networks-on-Chip

2013 ◽  
Vol 4 (3) ◽  
pp. 25-41
Author(s):  
Khalid Latif ◽  
Amir-Mohammad Rahmani ◽  
Tiberiu Seceleanu ◽  
Hannu Tenhunen
Keyword(s):  
Critical Path ◽  
Network Interface ◽  
Path Delay ◽  
Traffic Patterns ◽  
Hop Count ◽  
Networks On Chip ◽  
Routing Strategy ◽  
Negative Exponential Distribution ◽  
On Chip ◽  
Negative Exponential

Partial Virtual channel Sharing (PVS) architecture has been proposed to enhance the performance of Networks-on-Chip (NoC) based systems. In this paper, the authors present an efficient and reliable Network Interface (NI) assisted routing strategy for NoC using PVS architecture. For this purpose, NoC system is divided into clusters. Each cluster is a group of two nodes comprising Processing Elements (PE), switches, links, etc. Each PE in a cluster can inject data to the network through a router, which is closer to the destination. This helps to reduce the network load by reducing the average hop count of the network. The proposed architecture can recover the PE disconnected from the network due to network level faults by allowing the PE to transmit and receive the packets through the other router in the cluster. 5×6 crossbar is used for the proposed architecture which requires one more 5×1 multiplexer without increasing the critical path delay of the router as compared to the 5×5 crossbar. The proposed router has been simulated for uniform, transpose and negative exponential distribution (NED) traffic patterns. The simulation results show the significant reduction in average packet latency at the expense of negligible area overhead.

Mapping multiple applications with unbounded and bounded number of cores on many-core networks-on-chip

2013 ◽  
Vol 37 (4-5) ◽  
pp. 460-471 ◽  
Author(s):  
Bo Yang ◽  
Liang Guang ◽  
Tero Säntti ◽  
Juha Plosila
Keyword(s):  
Networks On Chip ◽  
Core Networks ◽  
Bounded Number ◽  
On Chip ◽  
Many Core

scholarly journals A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 183
Author(s):  
Jose Ricardo Gomez-Rodriguez ◽  
Remberto Sandoval-Arechiga ◽  
Salvador Ibarra-Delgado ◽  
Viktor Ivan Rodriguez-Abdala ◽  
Jose Luis Vazquez-Avila ◽  
...  
Keyword(s):  
Single Chip ◽  
Synthesis Time ◽  
Networks On Chip ◽  
Data Dependencies ◽  
Layered Architecture ◽  
Systems On Chip ◽  
Challenges And Opportunities ◽  
Computing Platforms ◽  
On Chip ◽  
Many Core

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

scholarly journals A Latency-Optimized Network-on-Chip with Rapid Bypass Channels

Micromachines ◽  
2021 ◽  
Vol 12 (6) ◽  
pp. 621
Author(s):  
Wenheng Ma ◽  
Xiyao Gao ◽  
Yudi Gao ◽  
Ningmei Yu
Keyword(s):  
Great Reduction ◽  
Network On Chip ◽  
Traffic Patterns ◽  
Single Cycle ◽  
High Bandwidth ◽  
On Chip

Network-on-Chips with simple topologies are widely used due to their scalability and high bandwidth. The transmission latency increases greatly with the number of on-chip nodes. A NoC, called single-cycle multi-hop asynchronous repeated traversal (SMART), is proposed to solve the problem by bypassing intermediate routers. However, the bypass setup request of SMART requires additional pipeline stages and wires. In this paper, we present a NoC with rapid bypass channels that integrates the bypass information into each flit. In the proposed NoC, all the bypass requests are delivered along with flits at the same time reducing the transmission latency. Besides, the bypass request is unicasted in our design instead of broadcasting in SMART leading to a great reduction in wire overhead. We evaluate the NoC in four synthetic traffic patterns. The result shows that the latency of our proposed NoC is 63.54% less than the 1-cycle NoC. Compared to SMART, more than 80% wire overhead and 27% latency are reduced.

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