Implementation and Evaluation of Skip-Links

The Skip-link architecture dynamically reconfigures Network-on-Chip (NoC) topologies in order to reduce the overall switching activity in many-core systems. The proposed architecture allows the creation of long-range Skip-links at runtime to reduce the logical distance between frequently communicating nodes. This offers a number of advantages over existing methods of creating optimised topologies already present in research, such as the Reconfigurable NoC (ReNoC) architecture and static Long-Range Link (LRL) insertion. This architecture monitors traffic behaviour and optimises the mesh topology without prior analysis of communications behaviour, and is thus applicable to all applications. The technique described here does not utilise a master node, and each router acts independently. The architecture is thus scalable to future many-core networks. The authors evaluate the performance using a cycle-accurate simulator with synthetic traffic patterns and compare the results to a mesh architecture, demonstrating logical hop count reductions of 12-17%. Coupled with this, up to a doubling in critical load is observed, and the potential for 10% energy reductions on a 16×16 node network.

Adoption of Model-Based Testing and Abstract Interpretation by a Railway Signalling Manufacturer

Introduction of formal model-based practices into the development process of a product in a company implicates changes in the verification and validation activities. A testing process that focuses only on code is not comprehensive in a framework where the building blocks of development are models, and industry is currently heading toward more effective strategies to cope with this new reality. This paper reports the experience of a railway signalling manufacturer in changing its unit level verification process from code-based testing to a two-step approach comprising model-based testing and abstract interpretation. Empirical results on different projects, on which the overall development process was progressively tuned, show that the change paid back in terms of verification cost reduction (about 70%), bug detection, and correction capability.

Model-Based Testing of Highly Configurable Embedded Systems in the Automation Domain

This article reports the results of an industrial case study demonstrating the efficacy of a model-based testing process in assuring the quality of highly configurable systems from the automation domain. Escalating demand for flexibility has made modern embedded software systems highly configurable. This configurability is often realized through parameters and a highly configurable system possesses a handful of those. Small changes in parameter values can account for significant changes in the system’s behavior, whereas in other cases, changed parameters may not result in any perceivable reaction. This case study addresses the challenge of applying model-based testing to configurable embedded software systems to reduce development effort. As a result of the case study, a model-based testing process was developed and tailored toward the needs of the automation domain. This process integrates existing model-based testing methods and tools, such as combinatorial design and constraint processing. The testing process was applied as part of the case study and analyzed in terms of its actual saving potentials, which reduced the testing effort by more than a third.

Checkpointing SystemC-Based Virtual Platforms

The ability to restore a virtual platform from a previously saved simulation state can considerably shorten the typical edit-compile-debug cycle for software developers and therefore enhance productivity. For SystemC based virtual platforms (VP), dedicated checkpoint/restore (C/R) solutions are required, taking into account the specific characteristics of such platforms. Apart from restoring the simulation process from a checkpoint image, the proposed checkpoint solution also takes care of re-attaching debuggers and interactive GUIs to the restored virtual platform. The checkpointing is handled automatically for most of the SystemC modules, only the usage of host OS resources requires user provision. A process checkpointing based C/R has been selected in order to minimize the adaption required for existing VPs at the expense of large checkpoint sizes. This drawback is overcome by introducing an online compression to the checkpoint process. A case study based on the SHAPES Virtual Platform is conducted to investigate the applicability of the proposed framework as well as the impact of checkpoint compression in a realistic system environment.

Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design

Source synchronous links for use in multi-synchronous networks-on-chip (NoCs) are becoming the most vulnerable points for correct network operation and must be safeguarded against intra-link delay variations and signal misalignments. The intricacy of matching link net attributes during placement and routing and the growing role of process parameter variations in nanoscale silicon technologies are the root causes for this. This article addresses the challenge of designing a process variation and layout mismatch tolerant link for synchronizer-based GALS NoCs by implementing a self-calibration mechanism. A variation detector senses the variability-induced misalignment between data lines with themselves and with the transmitter clock routed with data in source synchronous links. A suitable delayed replica of the transmitter clock is then selected for safe sampling of misaligned data. The manuscript proves robustness of the link in isolation with respect to a detector-less link, but also assesses integration issues with the downstream synchronizer and switch architecture, proving the benefits in a realistic experimental setting for cost-effective NoCs.

Asymmetric Geographic Forwarding

Geographic Forwarding (GF) algorithms typically employ a neighbor discovery method to maintain a neighborhood table that works well only if all wireless links are symmetric. Recent experimental research has revealed that the link conditions in realistic wireless networks vary significantly from the ideal disk model and a substantial percentage of links are asymmetric. Existing GF algorithms fail to consider asymmetric links in neighbor discovery and thus discount a significant number of potentially stable routes with good one-way reliability. This paper introduces Asymmetric Geographic Forwarding (A-GF), which discovers asymmetric links in the network, evaluates them for stability (e.g., based on mobility), and uses them to obtain more efficient and shorter routes. A-GF also successfully identifies transient asymmetric links and ignores them to further improve the routing efficiency. Comparisons of A-GF to the original GF algorithm and another related symmetric routing algorithm indicate a decrease in hop count (and therefore latency) and an increase in successful route establishments, with only a small increase in overhead.

Cost-Based Topology Optimization of Embedded Ethernet Networks

During past decades, Ethernet progressively became the most widely used Local Area Network (LAN) technology. Apart from LAN installations, Ethernet also became attractive for other application areas such as industrial control, automotive, and avionics. In traditional LAN design, the objective is to minimize the network deployment cost. However, in embedded networks, additional constraints and ambient conditions add to the complexity of the problem. In this paper, the authors propose a Simulated Annealing (SA) algorithm to optimize the physical topology of an embedded Ethernet network. The various constraints and ambient conditions are modeled by a cost map. For networks with small number of nodes and/or switches, the authors were able to find the optimal solutions using adapted algorithms. These solutions will serve as a lower bound for the solutions obtained via the SA algorithm. However, the adapted algorithms are time consuming and application specific. The paper shows that the SA algorithm can be applied in all cases and finds (near-) optimal solutions.

Optimized Communication Architecture of MPSoCs with a Hardware Scheduler

Efficient runtime resource management in multi-processor systems-on-chip (MPSoCs) for achieving high performance and low energy consumption is one of the key challenges for system designers. OSIP, an operating system application-specific instruction-set processor, together with its well-defined programming model, provides a promising solution. It delivers high computational performance to deal with dynamic task scheduling and mapping. Being programmable, it can easily be adapted to different systems. However, the distributed computation among the different processing elements introduces complexity to the communication architecture, which tends to become the bottleneck of such systems. In this work, the authors highlight the vital importance of the communication architecture for OSIP-based systems and optimize the communication architecture. Furthermore, the effects of OSIP and the communication architecture are investigated jointly from the system point of view, based on a broad case study for a real life application (H.264) and a synthetic benchmark application.

Requirements Traceability within Model-Based Testing

Requirements traceability enables the linkage between all development artifacts during the development process. Within model-based testing, requirements traceability links the original requirements with test model elements and generated test cases. Current approaches are either not practical or lack the necessary formal foundation for generating requirements-based test cases using model-checking techniques involving the requirements trace. This paper describes a practical and formal approach to ensure requirements traceability. The descriptions of the requirements are defined on path fragments of timed automata or timed state charts. The graphical representation of these paths is called a computation sequence chart (CSC). CSCs are automatically transformed into temporal logic formulae. A model-checking algorithm considers these formulae when generating test cases.

Analysis of Monitoring Structures for Network-on-Chip

Monitoring services are essential for advanced, reliable NoC systems. They should support traffic management, system reconfiguration and fault detection to enable optimal performance and reliability of the system. The paper presents a thorough description of NoC monitoring structures and studies earlier works. A distributed monitoring structure is proposed and compared against the structures presented in previous works. The proposed distributed network monitoring system does not require centralized control, is fully scalable and does not cause significant traffic overhead to the network. The distributed structure is in line with the scalability and flexibility of the NoC paradigm. The paper studies the monitoring structure features and analyzes traffic overhead, monitoring data diffusion, cost and performance. The advantages of distributed monitoring are found evident and the limitations of the structure are discussed.