Vertical Planting Structure Design for Planter

2014 ◽  
Vol 654 ◽  
pp. 87-90
Author(s):  
Deng Quan Zhang ◽  
Yan Juan Wu ◽  
Chuang Kai Zhang
Keyword(s):  
Structure Design ◽  
Vertical Planting ◽  
Plant Efficiency

In view of many garlic drills without vertical planting structure so far, garlic clove cannot be vertical planted. A new design of vertical planting structure is proposed. The gripper for fixing garlic clove is designed. Moreover, the accurate cooperation is realized both transfer and vertical planting for garlic clove. Garlic clove is vertically inserted into the appropriate depth soil using the proposed machine. The structure of the proposed device is simple. It is convenient also to operate the device. The whole design of device is clever and cooperate appropriately. It can automatically operate from garlic clove fixing and transferring to garlic clove upright planting into appropriate depth soil. The effectiveness and feasibility of the proposed device is proved by lots of experiments. The result shown that the proposed device greatly improve plant efficiency, greatly improve the garlic budding rate, and effectively prevent the phenomenon of abnormal buds.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

Spatial Database Structure Design of Regional Geology Annals of China

2012 ◽  
Vol 13 (6) ◽  
pp. 720-726 ◽  
Author(s):  
Benxian FAN ◽  
Qinghe ZHANG ◽  
Yuanjing JU ◽  
Kunying HAN ◽  
Lan JIANG ◽  
...  
Keyword(s):  
Spatial Database ◽  
Structure Design ◽  
Regional Geology ◽  
Database Structure
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