A Real-Time Sequence Detection Algorithm for Floating Point Unit Design

2014 ◽  
Vol 687-691 ◽  
pp. 3494-3497
Author(s):  
Wei Sun ◽  
Jun She An ◽  
Shuang Yang

Sequence detection is used in many algorithms and applications. Sequences are different depending on different demands. In the process of floating-point CORDIC coprocessor design,data are need to change from floating point format to fixed point format. This process is necessary to detect the number of consecutive zeros. We design the leading-zero-counting algorithm to achieve this function, and this conversion process is completed in a very fixed short time, to ensure the needs of the floating point CORDIC coprocessor.

2018 ◽  
Vol 7 (2.20) ◽  
pp. 14
Author(s):  
B Srikanth ◽  
M Siva Kumar ◽  
K Hari Kishore

In this paper, the single precision float point multiplication is performed using the Schonhage Strassen Algorithm. There are several types of floating point multiplications like Karatsubha and Toom cook. The Schonhage Strassen algorithm is conventionally a fixed point integer multiplication algorithm. The main advantage of the Schonhage Strassen multiplication is that, the multiplication of integer values greater than 5 digits ranging from 2215 to 2217 bit values proves to be efficient. The validation of the proposed floating point multiplication is done using FPGA real time implementation. The analysis of parameters like area and power are evaluated.  


Currently in the real-time audio applications fixed point CODEC is being used. But the major disadvantage of such CODEC is the speed and accuracy. Because , as the DSP systems cannot be operated with real-time signal ‘t’, but they can be operated with the discrete time ‘n’ , the real-time analog signal x(t) is to be converted into discrete time signal x(n) by the analog to digital convert (ADC). The most widely used ADC in the signal processing environment is sigma-delta ADC. But, it can operate with the maximum speed of 1MHz. The DSP processor can give several times more speed than sigma-delta ADC. Hence, the speed of DSP system is being limited by sigma-delta ADC, even though the DSP system has the capability to operate with great speed. Similarly, the accuracy is being missed because the floating point samples are converted into fixed point to get the compatibility with fixed point DSP processor. To eliminate these two bottlenecks the novel design methodology has been proposed in which the ADC and DAC have been eliminated and the system is developed by the 16 bit floating point.


2011 ◽  
Vol 60 (7) ◽  
pp. 913-922 ◽  
Author(s):  
Sameh Galal ◽  
Mark Horowitz

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