Implementation of Audio CODEC with a Novel Design Methodology

Currently in the real-time audio applications fixed point CODEC is being used. But the major disadvantage of such CODEC is the speed and accuracy. Because , as the DSP systems cannot be operated with real-time signal ‘t’, but they can be operated with the discrete time ‘n’ , the real-time analog signal x(t) is to be converted into discrete time signal x(n) by the analog to digital convert (ADC). The most widely used ADC in the signal processing environment is sigma-delta ADC. But, it can operate with the maximum speed of 1MHz. The DSP processor can give several times more speed than sigma-delta ADC. Hence, the speed of DSP system is being limited by sigma-delta ADC, even though the DSP system has the capability to operate with great speed. Similarly, the accuracy is being missed because the floating point samples are converted into fixed point to get the compatibility with fixed point DSP processor. To eliminate these two bottlenecks the novel design methodology has been proposed in which the ADC and DAC have been eliminated and the system is developed by the 16 bit floating point.

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Design and Implementation ofReal-time Electrical Stimulation Artifact Suppression based on STM32

Turkish Journal of Computer and Mathematics Education (TURCOMAT) ◽

10.17762/turcomat.v12i5.982 ◽

2021 ◽

Vol 12 (5) ◽

pp. 424-427

Author(s):

Sangsoo Park, Hojun Yeom

Keyword(s):

Central Nervous System ◽

Nervous System ◽

Electrical Stimulation ◽

Embedded System ◽

Muscle Contraction ◽

Real Time ◽

High Performance ◽

Floating Point ◽

Time Signal ◽

Central Nervous System Damage

A biosignal is used as a control signal for electrical stimulation to restore weakened muscle function due to damage to the central nervous system. In patients with central nervous system damage, sufficient muscle contraction does not occur spontaneously. In this case, applying electrical stimulation can cause normal muscle contraction. However, it is necessary to remove the electrical stimulation artifact caused by the electrical stimulation. This paper describes a system design that removes electrical stimulation artifact in real time using a Cortex-M4-based STM32F processor. The STM32F is a very advantageous MCU for such DSPs, especially because it has a built-in floating point operator. Using STM32F's various high-performance peripherals (12-bit parallel ADC and 12-bit DAC, UART, Timer), an optimized embedded system was implemented.In this paper, the simulated and real-time results were compared and evaluated with the designed fir filter. In addition, the performance of the filter was evaluated through frequency analysis. As a result, it was verified that a high-performance 32-bit STM32F with floating point calculator and various peripherals is suitable for real-time signal processing

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A Real-Time Sequence Detection Algorithm for Floating Point Unit Design

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.687-691.3494 ◽

2014 ◽

Vol 687-691 ◽

pp. 3494-3497

Author(s):

Wei Sun ◽

Jun She An ◽

Shuang Yang

Keyword(s):

Fixed Point ◽

Real Time ◽

Detection Algorithm ◽

Time Sequence ◽

Floating Point ◽

Design Data ◽

Sequence Detection ◽

Unit Design ◽

Floating Point Unit ◽

Short Time

Sequence detection is used in many algorithms and applications. Sequences are different depending on different demands. In the process of floating-point CORDIC coprocessor design,data are need to change from floating point format to fixed point format. This process is necessary to detect the number of consecutive zeros. We design the leading-zero-counting algorithm to achieve this function, and this conversion process is completed in a very fixed short time, to ensure the needs of the floating point CORDIC coprocessor.

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Floating Point Multiplication Based on Schonhage Strassen Algorithm

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i2.20.11734 ◽

2018 ◽

Vol 7 (2.20) ◽

pp. 14

Author(s):

B Srikanth ◽

M Siva Kumar ◽

K Hari Kishore

Keyword(s):

Fixed Point ◽

Real Time ◽

Floating Point ◽

Single Precision ◽

Point Multiplication ◽

Multiplication Algorithm ◽

Integer Multiplication

In this paper, the single precision float point multiplication is performed using the Schonhage Strassen Algorithm. There are several types of floating point multiplications like Karatsubha and Toom cook. The Schonhage Strassen algorithm is conventionally a fixed point integer multiplication algorithm. The main advantage of the Schonhage Strassen multiplication is that, the multiplication of integer values greater than 5 digits ranging from 2215 to 2217 bit values proves to be efficient. The validation of the proposed floating point multiplication is done using FPGA real time implementation. The analysis of parameters like area and power are evaluated.

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Fixed-point vs. floating-point arithmetic comparison for adaptive optics real-time control computation

10.1117/12.787408 ◽

2008 ◽

Author(s):

Yolanda Martín-Hernando ◽

Luis F. Rodríguez-Ramos ◽

Marcos R. Garcia-Talavera

Keyword(s):

Fixed Point ◽

Real Time ◽

Adaptive Optics ◽

Floating Point ◽

Real Time Control ◽

Floating Point Arithmetic ◽

Time Control ◽

Point Arithmetic

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Discrete-time internal model control with disturbance and vibration rejection

Journal of Vibration and Control ◽

10.1177/1077546315601935 ◽

2016 ◽

Vol 23 (1) ◽

pp. 3-15 ◽

Cited By ~ 14

Author(s):

Robin De Keyser ◽

Cosmin Copot ◽

Andres Hernandez ◽

Clara Ionescu

Keyword(s):

Discrete Time ◽

Disturbance Rejection ◽

Internal Model ◽

Design Methodology ◽

Closed Loop ◽

Open Loop ◽

Internal Model Control ◽

Process Dynamics ◽

Model Control ◽

Novel Design

This paper presents a novel design methodology for discrete-time internal model control (IMC) used to compute a disturbance filter. The proposed method employs a generalized algorithm for disturbance rejection and for process dynamics compensation. In IMC, the controller is designed based on a model of the process, while ensuring a desired closed loop performance trajectory (for setpoint tracking). However, in some situations, for example poorly damped systems, the open loop poles of the process affect the closed loop disturbance rejection dynamics. The novel design methodology presented is able to compensate both process dynamics and input disturbances. The method is validated both in simulations and in experimental tests on a poorly damped mass–spring–damper testbench.

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Implementation of Parallel and Pipeline Scheme in the Standard Floating Point Adder to Improve the Speed

International Journal of Engineering and Advanced Technology - Regular Issue ◽

10.35940/ijeat.b4228.129219 ◽

2019 ◽

Vol 9 (2) ◽

pp. 3073-3076

Keyword(s):

Signal Processing ◽

Real Time ◽

Impulse Response ◽

Floating Point ◽

Infinite Impulse Response ◽

Time Signal ◽

Fir Filters ◽

Iir Filters ◽

In Series ◽

Floating Point Numbers

In real time Signal Processing applications, the analogue signal is over sampled as per the Nyquist criterion in order to avoid the aliasing effect. Floating Point (FP) adder is used in the floating point Multiplier Accumulator Content (MAC) for real time Digital Signal Processing(DSP) applications. The heart of any real time DSP processor is floating point MAC. Floating Point MAC is constructed by Finite Impulse Response (FIR) or Infinite Impulse Response (IIR) filters. FIR filters are stable than IIR filters because the impulse response is finite in FIR. Hence, for stable applications FIR filters are preferred. These FIR filters are intern constituted by FP adder, FP multiplier and shifter. In conventional floating point adder the two floating point numbers are added in series. Series means one after the other so the computation speed is less. In series fashion adding the floating point numbers means definitely it furnishes more delay[1] because in the addition of floating point numbers, along with the addition of mantissas; computation is required for both signs and exponents also. Hence, the processing speed is slow for computing the floating point numbers compared with fixed point numbers. Therefore, in order to increase the speed of operation for floating point addition in real time application i.e., to add 16- samples at a time which are in floating notation; a parallel and pipe line technique is going to be incorporated to the two bit floating point architecture. Before developing such novel architecture, a novel algorithm is developed and after, the novel architecture is developed. The total work is simulated by Modelsim 10.3c tool and synthesized by Xilinx 13.6 tool.

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