A Fully Integrated S-Band Power Amplifier in 0.35um-SiGe BiCMOS Technology

2011 ◽  
Vol 403-408 ◽  
pp. 2481-2484
Author(s):  
Kang Li ◽  
Guo Dong Huang ◽  
Xiao Feng Yang ◽  
Qian Feng ◽  
Chao Xian Zhu ◽  
...  
Keyword(s):  
Power Amplifier ◽  
High Efficiency ◽  
Small Signal ◽  
Two Stage ◽  
Fully Integrated ◽  
Matching Networks ◽  
Band Power ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
On Chip

A fully integrated S-band high efficiency power amplifier using the TSMC 0.35 um SiGe BiCMOS technology is presented. The two-stage power amplifier has been optimized for the whole S-band covering 2 GHz to 4 GHz frequency band for higher 1-dB compression point and efficiency. The input and output matching networks are designed on chip. From the simulate result, the two-stage power amplifier achieves high PAE of 28% and saturation output power of 23.3 dBm at 3 GHz, with the small signal gain of 18.7 dB. Besides, this PA realizes the PAE within the band of 2.4GHz to 4GHz exceed 25%, and the highest PAE of 30.6% at 3.4 GHz.

A 20dBm E-band power amplifier in SiGe BiCMOS technology

2012 ◽  
Author(s):  
Roee Ben Yishay ◽  
Roi Carmon ◽  
Oded Katz ◽  
Benny Sheinman ◽  
Danny Elad
Keyword(s):  
Power Amplifier ◽  
Band Power ◽  
Bicmos Technology ◽  
Sige Bicmos

Analysis and design of a high-gain 100–180-GHz differential power amplifier in 130 nm SiGe BiCMOS

2017 ◽  
Vol 9 (6) ◽  
pp. 1231-1239
Author(s):  
Faisal Ahmed ◽  
Muhammad Furqan ◽  
Klaus Aufinger ◽  
Andreas Stelzer
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
High Gain ◽  
Small Signal ◽  
Gain Bandwidth ◽  
Band Frequency ◽  
Analysis And Design ◽  
Differential Gain ◽  
Bicmos Technology ◽  
Sige Bicmos

This paper presents the design and measurement results of a high-gain D-band broadband power amplifier (PA) implemented in a 130 nm SiGe BiCMOS technology. The topology of the PA is based on four differential cascode stages with interstage matching networks. A detailed analysis of the frequency behavior of the transimpedance-gain of the common-base stage of the cascode is presented by means of small-signal equivalent circuits, when the proposed four-reactance wideband matching network is used for output matching to the subsequent stage. The effect of the size of the active devices, in achieving a desired gain, bandwidth, and output power, is investigated. The fabricated D-band amplifier is characterized on-wafer demonstrating a peak differential gain and output power of about 25 dB and 11 dBm, respectively, while utilizing a DC power of 262 mW from a 2.7 V supply. The 3-dB small-signal bandwidth of the PA spans from 100 to 180 GHz (limited by the measurement setup), making it the first SiGe-based PA to cover the entire D-band frequency range. The PA achieves a state-of-the-art differential gain-bandwidth product of around 1.4 THz and the highest GBW/PDCratio of 5.2 GHz/mW among all D-Band Si-based PAs.

A 18-dBm G-Band Power Amplifier using 130-nm SiGe BiCMOS Technology

2019 ◽  
Author(s):  
Abdul Ali ◽  
Paolo Colantonio ◽  
Franco Giannini ◽  
Dietmar Kissinger ◽  
Herman Jalli Ng ◽  
...  
Keyword(s):  
Power Amplifier ◽  
Band Power ◽  
Bicmos Technology ◽  
Sige Bicmos

122 GHz single-chip dual-channel SMD radar sensor with on-chip antennas for distance and angle measurements

2015 ◽  
Vol 7 (3-4) ◽  
pp. 407-414 ◽  
Author(s):  
Mekdes G. Girma ◽  
Markus Gonser ◽  
Andreas Frischen ◽  
Jürgen Hasch ◽  
Yaoming Sun ◽  
...  
Keyword(s):  
Building Blocks ◽  
Single Chip ◽  
Fully Integrated ◽  
Dual Channel ◽  
Angle Measurements ◽  
Bicmos Technology ◽  
Measurement Results ◽  
Sige Bicmos ◽  
On Chip ◽  
Digital Processor

This paper describes the design considerations, integration issues, packaging, and experimental performance of recently developed D-Band dual-channel transceiver with on-chip antennas fabricated in a SiGe-BiCMOS technology. The design comprises a fully integrated transceiver circuit with quasi-monostatic architecture that operates between 114 and 124 GHz. All analog building blocks are controllable via a serial peripheral interface to reduce the number of connections and facilitate the communication between digital processor and analog building blocks. The two electromagnetically coupled patch antennas are placed on the top of the die with 8.6 dBi gain and have a simulated efficiency of 60%. The chip consumes 450 mW and is wire-bonded into an open-lid 5 × 5 mm2quad-flat no-leads package. Measurement results for the estimation of range, and azimuth angle in single object situation are presented.

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