Measurements and analysis of different front-end configurations for monolithic SiGe BiCMOS pixel detectors for HEP applications

This paper presents a small-area monolithic pixel detector ASIC designed in 130 nm SiGe BiCMOS technology for the upgrade of the pre-shower detector of the FASER experiment at CERN. The purpose of this prototype is to study the integration of fast front-end electronics inside the sensitive area of the pixels and to identify the configuration that could satisfy at best the specifications of the experiment. Self-induced noise, instabilities and cross-talk were minimised to cope with the several challenges associated to the integration of pre-amplifiers and discriminators inside the pixels. The methodology used in the characterisation and the design choices will also be described. Two of the variants studied here will be implemented in the pre-production ASIC of the FASER experiment pre-shower for further tests.

A massively scalable Time-to-Digital Converter with a PLL-free calibration system in a commercial 130 nm process

A 33.6 ps LSB Time-to-Digital converter was designed in 130 nm BiCMOS technology. The core of the converter is a differential 9-stage ring oscillator, based on a multi-path architecture. A novel version of this design is proposed, along with an analytical model of linearity. The model allowed us to understand the source of the performance superiority (in terms of linearity) of our design and to predict further improvements. The oscillator is integrated in a event-by-event self-calibration system that allows avoiding any PLL-based synchronization. For this reason and for the compactness and simplicity of the architecture, the proposed TDC is suitable for applications in which a large number of converters and a massive parallelization are required such as High-Energy Physics and medical imaging detector systems. A test chip for the TDC has been fabricated and tested. The TDC shows a DNL≤1.3 LSB, an INL≤2 LSB and a single-shot precision of 19.5 ps (0.58 LSB). The chip dissipates a power of 5.4 mW overall.

A 5–50 GHz SiGe BiCMOS Linear Transimpedance Amplifier with 68 dBΩ Differential Gain towards Highly Integrated Quasi-Coherent Receivers

Quasi-coherent optical receivers have recently emerged targeting access networks, offering improved sensitivity and reach over direct-detection schemes at the expense of a higher receiver bandwidth. Higher levels of system integration together with sufficiently wideband front-end blocks, and in particular high-speed linear transimpedance amplifiers (TIAs), are currently demanded to reduce cost and scale up receiver data rates. In this article, we report on the design and testing of a linear TIA enabling high-speed quasi-coherent receivers. A shunt-feedback loaded common-base topology is adopted, with gain control provided by a subsequent Gilbert cell stage. The circuit was fabricated in a commercial 130 nm SiGe BiCMOS technology and has a bandpass characteristic with a 3 dB bandwidth in the range of 5–50 GHz. A differential transimpedance gain of 68 dBΩ was measured, with 896 mVpp of maximum differential output swing at the 1 dB compression point. System experiments in a quasi-coherent receiver demonstrate an optical receiver sensitivity of −30.5 dBm (BER = 1 × 10−3) at 10 Gbps, and −26 dBm (BER = 1 × 10−3) at 25 Gbps. The proposed TIA represents an enabling component towards highly integrated quasi-coherent receivers.

An E-band Variable Gain Amplifier with 24 dB-control range and 80 to 100 GHz 1 dB bandwidth in SiGe BiCMOS technology

Analysis, design, and characterization of an E-band Variable Gain Amplifier (VGA) in SiGe BiCMOS commercial technology is presented. VGA topologies are compared in terms of their capability to contribute to receiver linearity and dynamic range. The proposed VGA is based on a Gilbert multiplier cell exploiting current cancellation to enhance control range and linearity. A 1 dB bandwidth ranging from 80 to 100 GHz, a 24 dB gain control range and a −11.5 dBm input 1 dB compression point have been measured.

Phase and Amplitude Control Integrated Circuit in 0.18 μm SiGe BiCMOS for Sub-6 GHz Phased Array Applications

This paper presents simulation results of the C-band transmit/receive (Tx/Rx) phased-arrays integrated circuit (IC) for sub-6 GHz communication links. It is based on 0.18 μm SiGe BiCMOS technology. Phase and amplitude control IC consists of one Tx/Rx channel. Digitally controlled phase shifter allows adjusting relative phase of the output microwave signal in the range from 0 to 360 degrees with 5.625 degree step (6-bit resolution). Digitally controlled active attenuator provides the transfer ratio adjusting in the range from 0 to –31 dB with 1 dB step (5 bit resolution). Amplitude and phase correction system based on integrated temperature sensor, auxiliary 4-bit phase shifter, 4-bit attenuator and digital control unit is implemented. Correction in –60—85 °C temperature range with 5-bit resolu-tion is provided. The root mean square (rms) phase adjustment error does not exceed 1.6 degree. The rms attenuation error does not exceed 0.37 dB. The noise figure in Rx mode is below 6.5 dB. The output power in Tx mode is above 6 dBm at P1dB. The power consumption is 375 mW and 525 mW in Rx and Tx modes respectively.