122 GHz single-chip dual-channel SMD radar sensor with on-chip antennas for distance and angle measurements

2015 ◽  
Vol 7 (3-4) ◽  
pp. 407-414 ◽  
Author(s):  
Mekdes G. Girma ◽  
Markus Gonser ◽  
Andreas Frischen ◽  
Jürgen Hasch ◽  
Yaoming Sun ◽  
...  
Keyword(s):  
Building Blocks ◽  
Single Chip ◽  
Fully Integrated ◽  
Dual Channel ◽  
Angle Measurements ◽  
Bicmos Technology ◽  
Measurement Results ◽  
Sige Bicmos ◽  
On Chip ◽  
Digital Processor

This paper describes the design considerations, integration issues, packaging, and experimental performance of recently developed D-Band dual-channel transceiver with on-chip antennas fabricated in a SiGe-BiCMOS technology. The design comprises a fully integrated transceiver circuit with quasi-monostatic architecture that operates between 114 and 124 GHz. All analog building blocks are controllable via a serial peripheral interface to reduce the number of connections and facilitate the communication between digital processor and analog building blocks. The two electromagnetically coupled patch antennas are placed on the top of the die with 8.6 dBi gain and have a simulated efficiency of 60%. The chip consumes 450 mW and is wire-bonded into an open-lid 5 × 5 mm2quad-flat no-leads package. Measurement results for the estimation of range, and azimuth angle in single object situation are presented.

A Fully Integrated S-Band Power Amplifier in 0.35um-SiGe BiCMOS Technology

2011 ◽  
Vol 403-408 ◽  
pp. 2481-2484
Author(s):  
Kang Li ◽  
Guo Dong Huang ◽  
Xiao Feng Yang ◽  
Qian Feng ◽  
Chao Xian Zhu ◽  
...  
Keyword(s):  
Power Amplifier ◽  
High Efficiency ◽  
Small Signal ◽  
Two Stage ◽  
Fully Integrated ◽  
Matching Networks ◽  
Band Power ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
On Chip

A fully integrated S-band high efficiency power amplifier using the TSMC 0.35 um SiGe BiCMOS technology is presented. The two-stage power amplifier has been optimized for the whole S-band covering 2 GHz to 4 GHz frequency band for higher 1-dB compression point and efficiency. The input and output matching networks are designed on chip. From the simulate result, the two-stage power amplifier achieves high PAE of 28% and saturation output power of 23.3 dBm at 3 GHz, with the small signal gain of 18.7 dB. Besides, this PA realizes the PAE within the band of 2.4GHz to 4GHz exceed 25%, and the highest PAE of 30.6% at 3.4 GHz.

Fully Integrated Single-Chip 305–375-GHz Transceiver With On-Chip Antennas in SiGe BiCMOS

2018 ◽  
Vol 8 (3) ◽  
pp. 329-339 ◽  
Author(s):  
Jidan Al-Eryani ◽  
Herbert Knapp ◽  
Jonas Kammerer ◽  
Klaus Aufinger ◽  
Hao Li ◽  
...  
Keyword(s):  
Single Chip ◽  
Fully Integrated ◽  
Sige Bicmos ◽  
On Chip

Analysis and Design of On-Chip RF Interconnect Line for Wideband True-Time Delay Line Application

2021 ◽  
pp. 2150146
Author(s):  
Yang Chen ◽  
Zhaoyang Qiu ◽  
Xiaofei Di ◽  
Xianqing Chen ◽  
Yu-Dong Zhang
Keyword(s):  
Time Delay ◽  
Delay Line ◽  
Delay Model ◽  
Analysis And Design ◽  
True Time Delay ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Relative Delay ◽  
True Time ◽  
On Chip

This paper presents the analytical resistance–capacitance–inductance–conductance (RLCG) model of the on-chip interconnect line (IL) based on its structure, and the proposed model can be used to design IL and analyze the delay characteristics. Using electromagnetic (EM) simulation, the relations between the inductance, quality factor and the width, length of IL are obtained, which verifies the proposed RLCG model of IL. The delay model of IL is derived and verified with respect to the effects of the [Formula: see text] and [Formula: see text] by simulation, which can provide the benefit for the true-time delay line (TTDL) design using IL. This work proposes the experiments on the delay characteristics of 3-bit TTDL with IL based on 0.13[Formula: see text][Formula: see text]m SiGe BiCMOS technology. The group delay and transient delay of the TTDL are measured, which exhibits a maximal relative delay of 35 ps with an average of 5 ps delay resolution over a frequency range of 14–34[Formula: see text]GHz. The results are consistent with the delay analysis based on the proposed IL model.

scholarly journals 0.13 μm CMOS Traveling-Wave Power Amplifier with On- and Off-Chip Gate-Line Termination

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 133
Author(s):  
Aleksandr Vasjanov ◽  
Vaidotas Barzdenas
Keyword(s):  
Optical Communication ◽  
Traveling Wave ◽  
Communication Systems ◽  
Building Blocks ◽  
Power Added Efficiency ◽  
High Data ◽  
Operating Frequency Range ◽  
Measurement Results ◽  
Optical Communication Systems ◽  
On Chip

Broadband amplifiers are essential building blocks used in high data rate wireless, radar, and instrumentation systems, as well as in optical communication systems. Only a traveling-wave amplifier (TWA) provides sufficient bandwidth for broadband applications without reducing modern linearization techniques. TWA requires gate-line and drain-line termination, which can be implemented on- and off-chip. This article compares the performance of identical 0.13 μm CMOS TWAs, differing only in gate-line termination placement. Measurement results revealed that the designed TWAs with on- and off-chip termination have a bandwidth of 10 GHz with a maximum gain of 15 dB and a power-added efficiency (PAE) of 5%–22% in the whole operating frequency range. Placing the gate-line termination off-chip results in an S21 flatness reduction, compared to the gain of a TWA with on-chip termination. Gain fluctuation over frequency is reduced by 4–8 dB when the termination resistor is placed as an external circuit.

scholarly journals Microwave Photonic ICs for 25 Gb/s Optical Link Based on SiGe BiCMOS Technology

Symmetry ◽  
2019 ◽  
Vol 11 (12) ◽  
pp. 1453 ◽  
Author(s):  
Andrey A. Kokolov ◽  
Dmitry A. Konkin ◽  
Artyom S. Koryakovtsev ◽  
Feodor I. Sheyerman ◽  
Leonid I. Babak
Keyword(s):  
Extinction Ratio ◽  
Single Chip ◽  
Microwave Photonic ◽  
Half Wave Voltage ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Driver Amplifier ◽  
Integrated Transmitters ◽  
Optical Divider ◽  
Better Than

The design, simulation and experimental results of the integrated optical and electronic components for 25 Gb/s microwave photonic link based on a 0.25 µm SiGe:C BiCMOS technology process are presented. A symmetrical depletion-type Mach-Zehnder modulator (MZM) and driver amplifier are intended for electro-optical (E/O) integrated transmitters. The optical divider and combiner of MZM are designed based on the self-imaging theory and then simulated with EM software. In order to verify the correctness of the theory and material properties used in the simulation, a short test (prototype) MZM of 1.9 mm length is produced and measured. It shows an extinction ratio of 19 dB and half-wave voltage-length product of Vπ ∙ L = ~1.5 V·cm. Based on these results, the construction of the segmented modulator with several driver amplifier units is defined. The designed driver amplifier unit provides a bandwidth of more than 30 GHz, saturated output power of 6 dBm (output voltage of Vpp = 1.26 V), and matching better than −15 dB up to 35 GHz; it dissipates 170 mW of power and occupies an area of 0.4 × 0.38 mm2. The optical-electrical (O/E) receiver consists of a Ge-photodiode, transimpedance amplifier (TIA), and passive optical structures that are integrated on a single chip. The measured O/E 3 dB analog bandwidth of the integrated receiver is 22 GHz, and output matching is better than −15 dB up to 30 GHz, which makes the receiver suitable for 25 Gb/s links with intensity modulation. The receiver operates at 1.55 μm wavelength, uses 2.5 V and 3.3 V power supplies, dissipates 160 mW of power, and occupies an area of 1.46 × 0.85 mm2.

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