A Clock Optimization Method in the Digital Zooming of the Image Signal Processing System

2014 ◽  
Vol 981 ◽  
pp. 315-318
Author(s):  
Dong Li ◽  
Xiao Li Wang ◽  
Si Mon Chi ◽  
Chang Rui Zhao ◽  
Bin Yang
Keyword(s):  
Signal Processing ◽  
Power Consumption ◽  
Digital Image ◽  
Processing System ◽  
Optimization Method ◽  
Clock Frequency ◽  
Signal Processing System ◽  
Image Zooming ◽  
Digital Zooming

We address the problem of producing an enlarged picture from a given digital image (zooming). We propose a method that tries to take into account the difficulty to apply the very fast clock in the digital zooming unit of an ISP system. The ISP system hardware is realized in the FPGA and the zooming algorithm is parabola interpolation architecture. This paper presents an optimization method by using a synchronization FIFO to greatly reduce the clock frequency of the digital zooming unit, and by this the power consumption is also decreased significantly.

Design of Virtex-7 FPGA-Based High-Speed Signal Processor Carrier Board

2015 ◽  
Vol 719-720 ◽  
pp. 534-537
Author(s):  
Wen Hua Ye ◽  
Huan Li
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
High Speed ◽  
Processing System ◽  
Digital Signal ◽  
Signal Processing System ◽  
High Speed Adc ◽  
High Speed Data ◽  
Processor Speed ◽  
Signal Processor

With the development of digital signal processing technology, the demand on the signal processor speed has become increasingly high. This paper describes the hardware design of carrier board in high-speed signal processing module, which using Xilinx's newest Virtex-7 FPGA family XC7VX485T chip, and applying high-speed signal processing interface FMC to transport and communicate high-speed data between carrier board and daughter card with high-speed ADC and DAC. This design provides a hardware implementation and algorithm verification platform for high-speed digital signal processing system.

A High-Performance Signal Processing System for Monopulse Tracking Radar

2011 ◽  
Vol 383-390 ◽  
pp. 471-475
Author(s):  
Yong Bin Hong ◽  
Cheng Fa Xu ◽  
Mei Guo Gao ◽  
Li Zhi Zhao
Keyword(s):  
Signal Processing ◽  
High Performance ◽  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
Processing System ◽  
Digital Signal ◽  
Radar Signal ◽  
Signal Processing System ◽  
Parallel Pipelined ◽  
Tracking Radar

A radar signal processing system characterizing high instantaneous dynamic range and low system latency is designed based on a specifically developed signal processing platform. Instantaneous dynamic range loss is a critical problem when digital signal processing is performed on fixed-point FPGAs. In this paper, the problem is well resolved by increasing the wordlength according to signal-to-noise ratio (SNR) gain of the algorithms through the data path. The distinctive software structure featuring parallel pipelined processing and “data flow drive” reduces the system latency to one coherent processing interval (CPI), which significantly improves the maximum tracking angular velocity of the monopulse tracking radar. Additionally, some important electronic counter-countermeasures (ECCM) are incorporated into this signal processing system.

A DIGITAL FM SIGNAL PROCESSING SYSTEM FOR VCRs

2005 ◽  
Author(s):  
K. Hatanaka ◽  
Y. Shirasaki ◽  
N. Fujiwara ◽  
M. Watanabe ◽  
T. Furukawa
Keyword(s):  
Signal Processing ◽  
Processing System ◽  
Signal Processing System
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