scholarly journals IMPLEMENTATION OF RSA KEY GENERATION BASED ON RNS USING VERILOG

2012 ◽  
pp. 12-16
Author(s):  
VISHAK M ◽  
N. SHANKARAIAH
Keyword(s):  
Embedded System ◽  
Number System ◽  
Residue Number System ◽  
Key Generation ◽  
Verilog Hdl ◽  
Embedded Platform ◽  
High Processing Speed ◽  
Pair Generation ◽  
Level Parallelism ◽  
High Processing

RSA key generation is of great concern for implementation of RSA cryptosystem on embedded system due to its long processing latency. In this paper, a novel architecture is presented to provide high processing speed to RSA key generation for embedded platform with limited processing capacity. In order to exploit more data level parallelism, Residue Number System (RNS) is introduced to accelerate RSA key pair generation, in which these independent elements can be processed simultaneously. A cipher processor based on Transport Triggered Architecture (TTA) is proposed to realize the parallelism at the architecture level. In the meantime, division is avoided in the proposed architecture, which reduces the expense of hardware implementation remarkably. The proposed design is implemented by Verilog HDL and verified in matlab. A rate of 3 pairs per second can be achieved for 1024-bit RSA key generation at the frequency of 100 MHz.

scholarly journals Design and Implementation of RNS Filter using Modular-Multipliers

2019 ◽  
Vol 8 (9) ◽  
pp. 1325-1329
Keyword(s):  
Performance Metrics ◽  
Finite Impulse Response ◽  
Critical Path ◽  
Number System ◽  
Residue Number System ◽  
Path Delay ◽  
Clock Frequency ◽  
Verilog Hdl ◽  
Power Delay Product ◽  
Impulse Response Filter

In this paper, an efficient RNS based multiply-accumulate (MAC) unit is proposed to implement residue number system (RNS) based finite impulse response filter (FIR). The proposed MAC (PMAC) approach reduces the number of adders in critical path delay. In this work, a FIR filter with PMAC approach is implemented using structural Verilog HDL language. The United Microelectronics Corporation 90 nm technology library has been used for synthesis. The performance metrics such as area, power and delay are obtained using Cadence RTL compiler. The synthesis results shows that RNS filter with PMAC improves clock frequency and reduces delay and area when compared to conventional MAC (CMAC).To compare the performance of the filters power delay product (PDP) is also considered. The PMAC architecture has improved PDP gain by 30.63% when compared to CMAC.

scholarly journals HDL Implementation of Five Moduli Residue Number System

2019 ◽  
Vol 8 (9) ◽  
pp. 689-693
Keyword(s):  
High Speed ◽  
Fault Tolerant ◽  
Number System ◽  
Residue Number System ◽  
Verilog Hdl ◽  
Forward Converter ◽  
Half Adder ◽  
Ripple Carry Adder ◽  
Residue Number ◽  
Day By Day

The demand for residue number system (RNS) is increasing day by day because of its high speed and fault tolerant characteristics. RNS encodes a large number into group of small numbers, which consequently increases the overall data processing rate. This paper presents an analysis of the forward converter designed using ripple carry adder (RCA), carry save adder (CSA), and half adder-like (HAL), for the figure of merits area, delay, and power for five moduli set: 2n -1, 2n , 2n +1, 2n+1 -1, and 2n-1 -1 with the standard cells at 90 nm technology. The designing of different blocks has been done in Verilog-HDL. The area, delay, and power of the implemented circuits are obtained using the Synopsys Design Compiler at 90 nm technology node, while VCS is used for verification. It is observed that the area of the architecture using CSA is less, whereas power utilization and timing behavior are better in HAL.

scholarly journals Implementation three-step algorithm based on signed digit number system by using neural network

2021 ◽  
Vol 24 (3) ◽  
pp. 1832
Author(s):  
Qabeela Q. Thabit ◽  
Alyaa Ibragim Dawood ◽  
Bayadir A. Issa
Keyword(s):  
Neural Networks ◽  
High Efficiency ◽  
Arithmetic Operation ◽  
Number System ◽  
Arithmetic Circuit ◽  
Digit Number ◽  
High Processing Speed ◽  
Effective System ◽  
Step Algorithm ◽  
High Processing

The need for a simple and effective system that works with high efficiency features such as high processing speed, the ability to solve problems by learning method and accomplish the largest amount of data processing accurately and in little time produces that system, which attracted the efforts of the researcher to employ neural networks in computing away from the complexities that burden traditional computers. We presented a model for the design of the arithmetic circuit for the process of addition the sign digit numbers in a new way to deal with the arithmetic operations, which employment of the use of neural networks, this model includes a theoretical and practical simulation of them. The model relied on the implementation of the addition process based on a three-step algorithm adopted by the signed systems. Which is characterized by the possibility of execution in a parallel way, and therefore it provides the advantage of completion of arithmetic operation regardless of the length of their operands, or in other words, whatever the number of bits in the operands. The simulation of the model is done by entering operands for 6 addition operations (each one has operands are 15-bit length) to be executed simultaneously.

scholarly journals Montgomery reduction within the context of residue number system arithmetic

2017 ◽  
Vol 8 (3) ◽  
pp. 189-200 ◽  
Author(s):  
Jean-Claude Bajard ◽  
Julien Eynard ◽  
Nabil Merkiche
Keyword(s):  
Number System ◽  
Residue Number System ◽  
Residue Number ◽  
Montgomery Reduction

scholarly journals Computationally Efficient Approach to Implementation of the Chinese Remainder Theorem Algorithm in Minimally Redundant Residue Number System

2021 ◽  
Author(s):  
Mikhail Selianinau
Keyword(s):  
Chinese Remainder Theorem ◽  
Number System ◽  
Residue Number System ◽  
Computer Applications ◽  
Efficient Approach ◽  
Residue Modulo ◽  
Modern Computer ◽  
New Variant ◽  
Residue Number ◽  
Residue Code

AbstractIn this paper, we deal with the critical problem of performing non-modular operations in the Residue Number System (RNS). The Chinese Remainder Theorem (CRT) is widely used in many modern computer applications. Throughout the article, an efficient approach for implementing the CRT algorithm is described. The structure of the rank of an RNS number, a principal positional characteristic of the residue code, is investigated. It is shown that the rank of a number can be represented by a sum of an inexact rank and a two-valued correction to it. We propose a new variant of minimally redundant RNS, which provides low computational complexity for the rank calculation, and its effectiveness analyzed concerning conventional non-redundant RNS. Owing to the extension of the residue code, by adding the excess residue modulo 2, the complexity of the rank calculation goes down from $O\left (k^{2}\right )$ O k 2 to $O\left (k\right )$ O k with respect to required modular addition operations and lookup tables, where k equals the number of non-redundant RNS moduli.

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