Implementation of Braun Multiplier with Efficient Pyramidal Adder Structure for Arithmetic Applications

Multiplier plays key role in Signal Processing and VLSI based environment applications, as it consumes more power and area compared other devices. In real time applications power and area are important parameters. Multiplier is essential component as it occupies large area and consumes more power compared to any other element .we have so many adders to design multiplier .In this paper Pyramidal adders are used which uses half-adder and full-adder to increase the speed and to reduce the number of gates used in the multiplier, but delay is not decreased significantly. If we modify the Pyramidal adder with XNOR’s and MUX instead of normal half-adder and full-adder, such pyramidal adder uses less gates and delay is reduced compared normal 16-bit adder. The use of XNOR’s and MUX in Pyramidal adder reduces delay, as the MUX function is only select the output among inputs. The use of such pyramidal adder in multiplier delay can be decreased greatly.

Simulation of the characteristics of low-voltage gates on combined cylindrical surrounding gate field-effect nanotransistors

The applicability of the architecture of a nanoscale surrounding gate field-effect transistor with a combined cylindrical working area for low-voltage applications is discussed. At the same time, the licensed TCAD Sentaurus instrument and technological modeling system is used as a tool. The transistor architecture under consideration involves combining the working zones of n-channel and p-channel transistors with one common gate. At the same time, the efficiency of suppressing short-channel effects is maintained and a high level of transistor current is provided in the strong inversion mode. Based on this architecture, a TCAD model of the NAND gate has been developed, the design of which contains two independent surrounding gates one combined working area. The use of the proposed gate architecture makes it possible to reduce the number of required transistor structures per gate by three times. This leads to a decrease in the switched capacity and power dissipation. From the simulation results, the gate geometric parameters with a working area length of 25 nm and a diameter of 8.5 nm, which can function at control voltages of 0.5 V in the frequency range up to 20 GHz with high gain, are determined. The switching time delay is 0.81 ps. The TCAD model of a half-adder is developed in the basis 2NAND. According to the simulation results, the efficiency of the prototype, which performs binary code addition operations with a delay of 4.2 ps at a supply voltage of 0.5 V and a frequency of 20 GHz, is shown. The obtained results create a theoretical basis for the synthesis of low-voltage complex functional blocks with high performance and minimal occupied area, which meets modern requirements for digital applications.

Low Power, High Speed MUX Based Area Efficient Dadda Multiplier

The multiplier is a fundamental building block in most digital ICs’ arithmetic units. The multiplier architecture in modern VLSI circuits must meet the main parameters of low power, high speed, and small area requirements. In this paper, a 4-bit multiplier is constructed using the Dadda algorithm with enhanced Full and Half adder blocks to achieve a smaller size, lower power consumption, and minimum propagation delay. The Dadda Algorithm-designed multiplier is used in the first phase to reduce propagation delay while adding partial products in three stages provided by AND Gates. In the second phase, each stage of the Dadda tree algorithm is built with an enhanced Full and half adders to reduce the design area, propagation delay, and power consumption while still meeting the requirements of the current scenario by using MUX logic. In an average of Conventional array Multipliers, the proposed Dadda multiplier achieved an 84.68% reduction in delay, 70.89% reduction in power, 84.68% increase in Maximum Usable Frequency (MUF), and 95.55% reduction in Energy per Samples (EPS).

Integrated non-volatile plasmonic switches based on phase-change-materials and their application to plasmonic logic circuits

Integrated photonic devices or circuits that can execute both optical computation and optical data storage are considered as the building blocks for photonic computations beyond the von Neumann architecture. Here, we present non-volatile hybrid electro-optic plasmonic switches as well as novel architectures of non-volatile combinational and sequential logic circuits. The electro-optic switches consist of a plasmonic waveguide having a thin layer of a phase-change-material (PCM). The optical losses in the waveguide are controlled by changing the phase of the PCM from amorphous to crystalline and vice versa. The phase transition process in the PCM can be realized by electrical threshold switching or thermal conduction heating via external electrical heaters or the plasmonic waveguide metal itself as an integrated heater. We have demonstrated that all logic gates, a half adder circuit, as well as sequential circuits can be implemented using the plasmonic switches as the active elements. Moreover, the designs of the plasmonic switches and the logic operations show minimum extinction ratios greater than 20 dB, compact designs, low operating power, and high-speed operations. We combine photonics, plasmonics and electronics on the same platform to design an effective architecture for logic operations.