Modeling of a 200 KHz Bandwidth Low-pass Switch-capacitor Sigma-delta DAC with a Raised Spur-free Modulator

2017 ◽  
Vol 17 (5) ◽  
pp. 666-674
Author(s):  
Yaya Chen ◽  
Yan Han ◽  
Tianlin Cao ◽  
Xiaoxia Han ◽  
Ray C. C. Cheung ◽  
...  
Keyword(s):  
Sigma Delta ◽  
Switch Capacitor ◽  
Low Pass

scholarly journals Complex incremental ΣΔ ADC.

2021 ◽  
Author(s):  
Shaul Peker
Keyword(s):  
Order System ◽  
Cmos Process ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Channel Input ◽  
Switch Capacitor ◽  
Quadrature Phase ◽  
Different Types ◽  
Low Pass ◽  
Time Interleaved

This thesis examines the theory and design of incremental Sigma-Delta (ΣΔ) modulators when applied to complex oversampling analog-to-digital converters (ADCs). Two different types of approaches for the complex ADC are analysed and compared. The first system is a traditional complex bandpass over-sampling ADC with incremental (time limited) ΣΔ architecture. This system uses cross-coupling switch capacitor (SC) integrators and quadrature two channel inputs. The second system uses a low-pass architecture with time interleaved integrators. This system does not have a mismatch between the in-phase and quadrature phase (I/Q) output channels. The input is frequency shifted down to DC during the conversion. A graphical user interface (GUI) design toolbox was created to design and simulate the two types of systems. The bandpass second-order system was fabricated in an IBM 130nm CMOS process with a 83kHz two channel input and 10kHz bandwidth at an OSR of 24.

scholarly journals Complex incremental ΣΔ ADC.

2021 ◽  
Author(s):  
Shaul Peker
Keyword(s):  
Order System ◽  
Cmos Process ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Channel Input ◽  
Switch Capacitor ◽  
Quadrature Phase ◽  
Different Types ◽  
Low Pass ◽  
Time Interleaved

This thesis examines the theory and design of incremental Sigma-Delta (ΣΔ) modulators when applied to complex oversampling analog-to-digital converters (ADCs). Two different types of approaches for the complex ADC are analysed and compared. The first system is a traditional complex bandpass over-sampling ADC with incremental (time limited) ΣΔ architecture. This system uses cross-coupling switch capacitor (SC) integrators and quadrature two channel inputs. The second system uses a low-pass architecture with time interleaved integrators. This system does not have a mismatch between the in-phase and quadrature phase (I/Q) output channels. The input is frequency shifted down to DC during the conversion. A graphical user interface (GUI) design toolbox was created to design and simulate the two types of systems. The bandpass second-order system was fabricated in an IBM 130nm CMOS process with a 83kHz two channel input and 10kHz bandwidth at an OSR of 24.

A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback

2010 ◽  
Vol 45 (9) ◽  
pp. 1795-1808 ◽  
Author(s):  
Cho-Ying Lu ◽  
Marvin Onabajo ◽  
Venkata Gadde ◽  
Yung-Chung Lo ◽  
Hsien-Pu Chen ◽  
...  
Keyword(s):  
Time Domain ◽  
Continuous Time ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Low Pass ◽  
Order Continuous

Modeling of Superconducting First- and Second-Order Low-Pass Sigma-Delta Modulators

2005 ◽  
Vol 15 (2) ◽  
pp. 372-375 ◽  
Author(s):  
P. Magnusson ◽  
P. Lowenborg ◽  
A. Kidiyarova-Shevchenko
Keyword(s):  
Second Order ◽  
Sigma Delta ◽  
Sigma Delta Modulators ◽  
Low Pass

A continuous time low-pass sigma delta modulator implemented with transmission lines

2005 ◽  
Author(s):  
L. Hernandez ◽  
P. Rombouts ◽  
E. Prefasi ◽  
S. Paton ◽  
M. Garcia ◽  
...  
Keyword(s):  
Transmission Lines ◽  
Continuous Time ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Low Pass
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