Complex incremental ΣΔ ADC.

This thesis examines the theory and design of incremental Sigma-Delta (ΣΔ) modulators when applied to complex oversampling analog-to-digital converters (ADCs). Two different types of approaches for the complex ADC are analysed and compared. The first system is a traditional complex bandpass over-sampling ADC with incremental (time limited) ΣΔ architecture. This system uses cross-coupling switch capacitor (SC) integrators and quadrature two channel inputs. The second system uses a low-pass architecture with time interleaved integrators. This system does not have a mismatch between the in-phase and quadrature phase (I/Q) output channels. The input is frequency shifted down to DC during the conversion. A graphical user interface (GUI) design toolbox was created to design and simulate the two types of systems. The bandpass second-order system was fabricated in an IBM 130nm CMOS process with a 83kHz two channel input and 10kHz bandwidth at an OSR of 24.

Complex incremental ΣΔ ADC.

This thesis examines the theory and design of incremental Sigma-Delta (ΣΔ) modulators when applied to complex oversampling analog-to-digital converters (ADCs). Two different types of approaches for the complex ADC are analysed and compared. The first system is a traditional complex bandpass over-sampling ADC with incremental (time limited) ΣΔ architecture. This system uses cross-coupling switch capacitor (SC) integrators and quadrature two channel inputs. The second system uses a low-pass architecture with time interleaved integrators. This system does not have a mismatch between the in-phase and quadrature phase (I/Q) output channels. The input is frequency shifted down to DC during the conversion. A graphical user interface (GUI) design toolbox was created to design and simulate the two types of systems. The bandpass second-order system was fabricated in an IBM 130nm CMOS process with a 83kHz two channel input and 10kHz bandwidth at an OSR of 24.